A data transfer system including a first memory and a processor includes a second memory and a DMA controller. The processor performs RMW on data which has a size less than a cache line size and in which a portion of a cache line (a unit area of the first memory) is a write destination. Output target data is transferred from an I/O device to the second memory. Thereafter, the DMA controller transfers the output target data from the second memory to the first memory in one or a plurality of transfer unit sizes by which the number of occurrences of RMW is minimized.

Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One apparatus includes an input/output memory management unit (IOMMU) comprising: a plurality of memory-mapped input/output (MMIO) registers that map memory address spaces belonging to the IOMMU and at least a second IOMMU; and hardware control logic operative to: synchronize the plurality of MMIO registers of the at least the second IOMMU; receive, from a peripheral component endpoint coupled to the IOMMU, a direct memory access (DMA) request, the DMA request to a memory address space belonging to the at least the second IOMMU; access the plurality of MMIO registers of the IOMMU based on context data of the DMA request; and access, from the IOMMU, a function assigned to the memory address space belonging to the at least the second IOMMU based on the accessed plurality of MMIO registers.

A serial transmission controller for processing data transmissions between a memory and an external device is provided. The serial transmission controller includes a microcontroller, a scheduling unit, a transmission unit, and an interception control unit. The microcontroller obtains pipe data from the memory. The microcontroller reads a transfer request block from the memory according to the pipe data. The scheduling unit generates a transmission request according to the pipe data and the transfer request block. The transmission unit transmits a packet of the transfer request block according to the transmission request, and correspondingly generates a transmission response. When the interception control unit receives the transmission response, and the data length that has not been transmitted in the transfer request block is greater than 0, the interception control unit notifies the transmission unit to continue to transmit a next packet of the transfer request block.

Embodiments of the present description provide a data processing method and apparatus, and an edge device. A currently received message is written to a first area of a local disk, and upon writing the currently received message to the first area of the local disk, the currently received message is buffered to a cache. When an edge device is restarted, data in the cache may be restored according to data stored in the first area of the local disk.

A system include a main computing system, a first peripheral component, and a second peripheral component. The first peripheral component receives analog signals from a hardware elements in a first peripheral system and converts them digital signal values in a local memory. A local processor of the first peripheral component writes the signal values directly into a first memory space in the physical memory of main computing system using direct memory access. The main computing system uses the signal values to generate output signal values that it writes into a second memory space of the physical memory. A second peripheral component directly accesses the second memory space to read the output signal values, and writes the output signal values into a local memory. The second peripheral component generates output analog signals based on the output signal values and provides the analog signals to hardware elements of a second peripheral system.

A cache management mechanism is provided having a size that is independent of an overall storage capacity of a non-volatile memory (NVM). The cache management mechanism includes a first level map data structure arranged as a first-in-first-out (FIFO) buffer to list a plurality of host access commands sequentially received from a host device. Each command has an associated host tag value. A cache memory stores user data blocks associated with the commands. A second level map of the cache management mechanism correlates cache addresses with the host tag values. A processing core searches the FIFO buffer in an effort to match a logical address of an existing command to the logical address for a new command. If a match is found, the host tag value is used to locate the cache address for the requested data. If a cache miss occurs, the new command is forwarded to the NVM.

Methods, devices, and systems for determining an address in a physical memory which corresponds to a virtual address using a skewed-associative translation lookaside buffer (TLB) are described. A virtual address and a configuration indication are received using receiver circuitry. A physical address corresponding to the virtual address is output if a TLB hit occurs. A first subset of a plurality of ways of the TLB is configured to hold a first page size. The first subset includes a number of the ways based on the configuration indication. A physical address corresponding to the virtual address is retrieved from a page table if a TLB miss occurs, and at least a portion of the physical address is installed in a least recently used way of a subset of a plurality of ways the TLB, determined according to a replacement policy based on the configuration indication.

Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. In an example apparatus, an input/output (I/O) device can receive signaling that includes a command to write to or read data from an address corresponding to a non-persistent memory device, and can determine where to redirect the request. For example, the I/O device can determine to write or read data to and/or from the non-persistent memory device or the persistent memory device based at least in part on one or more characteristics of the data.

A data transfer system including a first memory and a processor includes a second memory and a DMA controller. The processor performs RMW on data which has a size less than a cache line size and in which a portion of a cache line (a unit area of the first memory) is a write destination. Output target data is transferred from an I/O device to the second memory. Thereafter, the DMA controller transfers the output target data from the second memory to the first memory in one or a plurality of transfer unit sizes by which the number of occurrences of RMW is minimized.

Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. In an example apparatus, an input/output (I/O) device can receive signaling that includes a command to write to or read data from an address corresponding to a non-persistent memory device, and can determine where to redirect the request. For example, the I/O device can determine to write or read data to and/or from the non-persistent memory device or the persistent memory device based at least in part on one or more characteristics of the data.