Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.

In one embodiment, a method includes selectively invalidating data stored in at least one cache line of a cache memory in response to a determination that a predetermined amount of time has passed since the at least one cache line was last accessed. The predetermined amount of time is shorter than a round-trip time to process a plurality of blocks of data stored sequentially to a ring buffer. In other embodiments, methods, systems, and computer program products are described for efficient use of cache memory using an expiration timer.

A cache management mechanism is provided having a size that is independent of an overall storage capacity of a non-volatile memory (NVM). The cache management mechanism includes a first level map data structure arranged as a first-in-first-out (FIFO) buffer to list a plurality of host access commands sequentially received from a host device. Each command has an associated host tag value. A cache memory stores user data blocks associated with the commands. A second level map of the cache management mechanism correlates cache addresses with the host tag values. A processing core searches the FIFO buffer in an effort to match a logical address of an existing command to the logical address for a new command. If a match is found, the host tag value is used to locate the cache address for the requested data. If a cache miss occurs, the new command is forwarded to the NVM.

In one embodiment, a method includes selectively invalidating data stored in at least one cache line of a cache memory of a processor in response to a determination that a predetermined amount of time has passed since the at least one cache line was last accessed. The predetermined amount of time is shorter than an average round-trip time for the processor to process a plurality of blocks of data stored sequentially to a ring buffer. In other embodiments, methods, systems, and computer program products are described for efficient use of cache memory using an expiration timer.

This disclosure generally relates to hypervisor memory virtualization. In an example, multiple page table stages may be used to provide a page table that may be used by a processor when processing a workload for a nested virtual machine. An intermediate (e.g., nested) hypervisor may request an additional page table stage from a parent hypervisor, which may be used to virtualize memory for one or more nested virtual machines managed by the intermediate hypervisor. Accordingly, a processor may use the additional page table stages to ultimately translate a virtual memory address for a nested virtual machine to a physical memory address.

This disclosure generally relates to hypervisor memory virtualization. In an example, translation lookaside buffer (TLB) invalidation requests may be selectively delivered to processors to which they relate or may be ignored by processors to which they do not relate, so as to minimize the processing overhead that may be ordinarily associated with such TLB invalidation requests. In another example, a TLB invalidation request may be suspended in order to enable a hypervisor to finish executing instructions relating to one or more TLB entries that would be affected by the TLB invalidation request.

This disclosure generally relates to hypervisor memory virtualization. Techniques disclosed herein improve peripheral component interconnect express (PCI-e) device interoperability with a virtual machine. As an example, when a direct-memory access request is received from a PCI-e device but the target memory is currently unmapped, an indication may be provided to a memory paging processor so as to page-in the memory, such that the PCI-e device may continue to function normally. In some examples, the access request may be buffered and replayed once the memory is paged-in, or the access request may be retried, among other examples.

Embodiments relate to enhancing a refresh PCI translation (RPCIT) instruction to refresh a translation lookaside buffer (TLB). A computer processor determines a request to purge a translation for a single frame of the TLB in response to executing an enhanced RPCIT instruction. The enhanced RPCIT instruction is configured to selectively perform one of a single-frame TLB refresh operation or a range-bounded TLB refresh operation. The computer processor determines an absolute storage frame based on a translation of a PCI virtual address in response to the request to purge a translation for a single frame of the TLB. The computer processor further performs the single-frame TLB refresh operation to purge the translation for the single frame.

In one embodiment, a method includes selectively invalidating data stored in at least one cache line of a cache memory of a processor in response to a determination that a predetermined amount of time has passed since the at least one cache line was last accessed. The predetermined amount of time is shorter than an average round-trip time for the processor to process a plurality of blocks of data stored sequentially to a ring buffer. In other embodiments, methods, systems, and computer program products are described for efficient use of cache memory using an expiration timer.

A reverse order submission system includes a first memory including a ring buffer, a second memory, and a processor in communication with the first memory. The processor includes a consumer processor and a producer processor, and the producer processor is configured to receive a batch of memory entries. Further, the producer processor is configured to identify a last memory entry in the batch that can be stored in an invalid value slot in the ring buffer, walk the ring buffer backwards, and store each respective memory entry in each respective slot from an end slot to the original slot in the ring buffer. The end slot is a slot associated with the final memory entry ending the batch of memory entries or a slot preceding a valid value slot.