Embodiments of the present disclosure provide a cache system and associated method. The cache system includes a first pipeline module including a first plurality of sequential processing phases for executing a plurality of operations. The first plurality of operations is executed in response to Input/Output (I/O) requests of a first plurality of types for the persistent storage device, and each of the first plurality of operations is a common operation for the I/O requests of at least two of the first plurality of types. The cache system also includes a control module configured to: determine a first type of a first pending processing I/O request for the persistent storage device, and in response to the first type being one of the first plurality of types, cause the first pipeline module to be executed to process the first pending processing I/O request.

Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.

Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.

A peripheral proxy subsystem provides routing mechanisms to allow multiple hosts to communicate with multiple functions, physical and virtual, of a single root I/O virtualization (SR-IOV) peripheral, which may include a physical function and a plurality of virtual functions associated with the physical function. The peripheral proxy subsystem, which may be embodied as a controller, includes a first endpoint interface; a second endpoint interface; and a single root controller interface configured to couple to the SR-IOV peripheral. The controller is configured to be able to present through the single root controller interface: a first subset of the plurality of virtual functions through a first cloned instance of the physical function at the first endpoint interface; and a second subset of the plurality of virtual functions through a second cloned instance of the physical function at the second endpoint interface.

Methods, devices, and systems for determining an address in a physical memory which corresponds to a virtual address using a skewed-associative translation lookaside buffer (TLB) are described. A virtual address and a configuration indication are received using receiver circuitry. A physical address corresponding to the virtual address is output if a TLB hit occurs. A first subset of a plurality of ways of the TLB is configured to hold a first page size. The first subset includes a number of the ways based on the configuration indication. A physical address corresponding to the virtual address is retrieved from a page table if a TLB miss occurs, and at least a portion of the physical address is installed in a least recently used way of a subset of a plurality of ways the TLB, determined according to a replacement policy based on the configuration indication.

A method for caching a data block stored on a first storage device and onto a second storage device including determining whether a data block being requested contains a first type of data, upon a condition in which the data block contains the first type of data, writing the data block to the second storage device and upon a condition in which the data block does not contain the first type of data, determining whether a correspondingly mapped block on the second storage device contains the first type of data, and only writing the data block to the second storage device upon a condition in which the correspondingly mapped block does not contain the first type of data.

Systems and methods for a direct memory access (DMA) operation are provided. The method includes receiving a host memory address by a device coupled to a computing device; storing the host memory address at a device memory by a DMA engine; receiving a packet at the device for the computing device; instructing the DMA engine by a device processor to retrieve the host memory address from the device memory; retrieving the host memory address by the DMA engine without the device processor reading the host memory address; and transferring the packet to the computing device by a DMA operation.

Embodiments relate to enhancing a refresh PCI translation (RPCIT) instruction to refresh a translation lookaside buffer (TLB). A computer processor determines a request to purge a translation for a single frame of the TLB in response to executing an enhanced RPCIT instruction. The enhanced RPCIT instruction is configured to selectively perform one of a single-frame TLB refresh operation or a range-bounded TLB refresh operation. The computer processor determines an absolute storage frame based on a translation of a PCI virtual address in response to the request to purge a translation for a single frame of the TLB. The computer processor further performs the single-frame TLB refresh operation to purge the translation for the single frame.

Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.

In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation in response to the store instruction being marked as high priority and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise.