A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive nonvolatile memory. Local controller manages communication between the DRAM cache and nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.

A page directory entry cache (PDEC) can be checked to potentially rule out one or more possible page sizes for a translation lookaside buffer (TLB) lookup. Information gained from the PDEC lookup can reduce the number of TLB checks required to conclusively determine if the TLB lookup is a hit or a miss.

The disclosed technology provides for off-loading dirty data from a volatile cache memory to multiple non-volatile memory devices responsive to detection of a power failure. The arrangement of the dirty data is describable by a cache image, which is reconstructed within the volatile memory from the non-volatile memory devices responsive to detection of power restoration following the power failure.

Indications of a minimum retention time and a maximum retention time in a cache comprising a first type of memory and a second type of memory are received from a host application for a first plurality of tracks, wherein the minimum retention time or the maximum retention time are not indicated for a second plurality of tracks. In response to accessing a track of the first plurality of tracks, the minimum retention time is set for the track for the first type of memory, and the maximum retention time is set for the track for the second type of memory.

A hybrid memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory. An address buffer on the module maintains a static, random-access memory (SRAM) cache of addresses for data cached in DRAM.

According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller selects, as a write mode, at least one of a first mode in which N-bit data is written per memory cell in the nonvolatile memory and a second mode in which M-bit data is written per memory cell in the nonvolatile memory as a write mode. N is equal to or larger than one. M is larger than N. The controller selects the second mode when a reception speed of data, which is received in accordance with acceptance of one or more write commands from the host, is equal to or slower than a threshold, and selects the first mode when the reception speed is faster than the threshold.

Methods and devices related to sharing data between computing devices are described. In an example, a method can include writing a first portion of data to a DRAM on a first computing device, receiving, via a radio of the first computing device, first signaling representing a request to share the first portion of data via a first processing resource of the first computing device with a second processing resource of a second computing device, determining at the first processing resource of the first computing device to share the first portion of data with the second processing resource of the second computing device based on at least one of: a command from a user or data representing user settings stored in non-volatile memory on the first computing device, and transmitting, via the radio of the first computing device, second signaling comprising the first portion of data to the second processing resource of the second computing device.

A controller, a memory system and an operating method thereof are disclosed. The controller controls a nonvolatile memory device and the nonvolatile memory includes a first memory module configured to store a plurality of pieces of map data read from the nonvolatile memory device; and a second memory module configured to cache map data having locality among map data received from the first memory module.

A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host-resident FTL mode of operation to ameliorate erroneous or potentially malicious access to the memory device.