A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.

A multi-memory apparatus that uses machine learning is described. The apparatus may include an interface controller, a non-volatile memory, and a volatile memory. The interface controller may cause the apparatus to receive a first command from a host device. The interface controller may cause the apparatus to communicate the first command to a machine learning engine and to circuitry configured to store and manage commands for the non-volatile memory and the volatile memory. The interface controller may further cause the apparatus to communicate a second command generated by the machine learning engine to the circuitry. The second command may be based on information determined by the machine learning engine during a training mode.

Methods, systems, and devices for quality-of-service information for a multi-memory system are described. An interface controller may receive a first command from a host device during a set of clock cycles. The first command may be received over a command bus that includes a pin, such as a command select pin configured for double data rate signaling. The interface controller may decode the first command based on a state of the command select pin during at least one clock cycle of the set of clock cycles. And the interface controller may determine quality-of-service information for a second command based on decoding the first command and on information, such as a plurality of bits, included in the first command.

Provided are a computer program product, system, and method for indicating extents of tracks in mirroring queues based on information gathered on tracks in extents in cache. Extent information on an extent of tracks in a cache indicated in an active cache list is processed in response to destaging a track from the active cache list to add to a demote list used to determine tracks to remove from the cache. The extent information is related to a number of modified tracks in an extent destaged from the active cache list. The extent information for the extent is used to determine one of a plurality of mirroring queues to indicate the extent including modified tracks. A mirroring queue having a higher priority than another mirroring queue is processed at a higher rate to determine extents of tracks to mirror from the cache to the secondary storage.

Provided are a computer program product, system, and method for indicating extents of tracks in mirroring queues based on information gathered on tracks in extents in cache. Extent information on an extent of tracks in a cache indicated in an active cache list is processed in response to destaging a track from the active cache list to add to a demote list used to determine tracks to remove from the cache. The extent information is related to a number of modified tracks in an extent destaged from the active cache list. The extent information for the extent is used to determine one of a plurality of mirroring queues to indicate the extent including modified tracks. A mirroring queue having a higher priority than another mirroring queue is processed at a higher rate to determine extents of tracks to mirror from the cache to the secondary storage.

Provided are a computer program product for managing tracks in a storage in a cache. An active track data structure indicates tracks in the cache that have an active status. An active bit in a cache control block for a track is set to indicate active for the track indicated as active in the active track data structure. In response to processing the cache control block, a determination is made, from the cache control block for the track, whether the track is active or inactive to determine processing for the cache control block.

Methods and systems for a networked storage system are provided. One method includes: generating, by a first node, a dummy entry in a storage location cache of the first node, the dummy entry associated with a read request received by the first node for data stored using a logical object owned by a second node; receiving, by the first node, an invalidation request to invalidate any storage location entry associated with the data, the invalidation request sent in response to the second node receiving a write request to modify the data; invalidating, by the first node, the dummy entry; receiving, by the first node, a response to the read request from the second node with the requested data; and replacing, by the first node, the dummy entry with a storage location entry and invalidating the storage location entry based on the invalidated dummy entry.

A method, computer program product, and computing system for receiving a flush request for a metadata page stored in a storage array of a multi-node storage system. The flush request may be queued on a flush request lock queue on at least one node of the multi-node storage system. One or more flush requests may be processed, via multiple nodes of the multi-node storage system, on the metadata page based upon, at least in part, the flush request lock queue.

The present invention provides a control method of a server, wherein the server includes a write buffer for temporarily storing data from an electronic device, the write buffer has a plurality of sectors, and the write buffer has a write pointer and a flush pointer; and the control method comprises: setting each sector to have one of a plurality of states comprising an empty state, a merging state, a need-flush state and a flushing state; and referring to a state of a specific sector indicted by the write pointer to determine if ignoring the specific sector to directly process a sector after the specific sector.

A memory system includes a first volatile memory having an access unit of a first bit width; a second volatile memory having an access unit of the first bit width and having a capacity larger than the first volatile memory; and a controller connected to the first and second volatile memories. The controller allocates a first address space having the first bit width as a unit to the first volatile memory, allocates a second address space having the first bit width as a unit to the second volatile memory, selects at least one of the first and second volatile memories based on a first address indicating a position in a third address space having a second bit width as a unit, calculates a second address in the address space allocated to the selected volatile memory, and accesses a position corresponding to the second address of the selected volatile memory.