A processing system selectively compresses cache lines at a cache or at a memory or encrypts cache lines at the memory based on evictions of entries mapping virtual-to-physical address translations from a translation lookaside buffer (TLB). Upon eviction of a TLB entry, the processing system identifies cache lines corresponding to the physical addresses of the evicted TLB entry and selectively compresses the cache lines to increase the effective storage capacity of the processing system or encrypts the cache lines to protect against vulnerabilities.

Techniques for storing data involve estimating a hit ratio of a digest cache associated with a target storage device, the digest cache recording a digest of data that is stored in the target storage device after preprocessing; generating, according to a determination that the hit ratio is lower than a predetermined threshold, a digest for target data to be stored and performing the preprocessing; and storing, according to a determination that the digest of the target data is missing in the digest cache, the preprocessed target data in the target storage device, and recording the digest of the target data in the digest cache. Such techniques can achieve good system performance in both cases of high data repetition and low data repetition.

The system can receive data to be written to a non-volatile memory in the distributed storage system. The received data can include a plurality of input segments. The system can assign consecutive logical block addresses (LBAs) to the plurality of input segments. The system can then compress the plurality of input segments to generate a plurality of fixed-length compressed segments, with each fixed-length compressed segment aligned with a physical block address (PBA) in a set of PBAs. The system compresses the plurality of input segments to enable an efficient use of storage capacity in the non-volatile memory. Next, the system can write the plurality of fixed-length compressed segments to a corresponding set of PBAs in the non-volatile memory. The system can then create, in a data structure, a set of entries which map the LBAs of the input segments to the set of PBAs. This data structure can be used later by the system when processing a read request including a LBA.

A method and apparatus of a device for resource management by using a hierarchy of resource management techniques with dynamic resource policies is described. The device terminates several misbehaving application programs when available memory on the device is running low. Each of those misbehaving application programs consumes more memory space than a memory consumption limit assigned to the application program. If available memory on the device is still low after terminating those misbehaving application programs, the device further sends memory pressure notifications to all application programs. If available memory on the device is still running low after sending the memory pressure notifications, the device further terminates background, idle, and suspended application programs. The device further terminates foreground application programs when available memory on the device is still low after terminating the background, idle, and suspended application programs.

Apparatuses, systems, and techniques to indicate storage to be compressed. In at least one embodiment, an application programming interface is performed to indicate storage to store information to be compressed.

Systems, apparatuses, and methods for implementing flexible dictionary sharing techniques for caches are disclosed. A set-associative cache includes a dictionary for each data array set. When a cache line is to be allocated in the cache, a cache controller determines to which set a base index of the cache line address maps. Then, a selector unit determines which dictionary of a group of dictionaries stored by those sets neighboring this set would achieve the most compression for the cache line. This dictionary is then selected to compress the cache line. An offset is added to the base index of the cache line to generate a full index in order to map the cache line to the set corresponding to this chosen dictionary. The compressed cache line is stored in this set with the chosen dictionary, and the offset is stored in the corresponding tag array entry.

A data processing system is provided comprising a cache system configured to transfer data between a processor and memory system. The cache system comprises a cache. When a block of data that is stored in the memory in a compressed form is to be loaded into the cache, the block of data is stored into a group of one or more cache lines of the cache and the associated compression metadata for the compressed block of data is provided as separate side band data.

According to one embodiment, a buffer stores first hash values and first complementary data. A first conversion unit converts consecutive characters in a second character string into second hash values and second complementary data. A search unit searches for consecutive first hash values from the buffer, and output a pointer. A selection unit selects consecutive first hash values and pieces of first complementary data from the buffer. A second conversion unit converts the consecutive first hash values into a third character string using the pieces of first complementary data. A comparison unit compares the second character string with the third character string to acquire a matching length. An output unit output the matching length with the pointer.

A method and system for compressing and decompressing data is disclosed. A compression command may initiate the prefetching of first data, which may be stored in a first buffer. Multiple words of the first data may be read from the first buffer and used to generate a plurality of compressed packets, each of which includes a command specifying a type of packet. The compressed packets may be combined into a group and multiple groups may be combined and stored in a second buffer. A decompression command may initiate the prefetching of second data, which is stored in the first buffer. A portion of the second data may be read from the first buffer and used to generate a group of compressed packets. Multiple output words may be generated dependent upon the group of compressed packets.

Techniques to improve performance of matrix multiply operations are described in which a compute kernel can specify one or more element-wise operations to perform on output of the compute kernel before the output is transferred to higher levels of a processor memory hierarchy.