Patent classifications
G06F2212/604
DATA PROCESSING METHOD AND DEVICE IN CACHE COHERENCE DIRECTORY ARCHITECTURE
The embodiment of the disclosure discloses a data processing method and device in a cache coherence directory architecture. The method includes that allocating a tag entry in a tag array for a data block; allocating a data entry in a data array for the data block when the data block is actively shared; and de-allocating the data entry when the data block is temporarily private or gets evicted in the data array. Therefore the embodiments of the disclosure allocate data entry only when a data block is actively shared and will not allocate data entry for data block which is not actively shared, therefore smaller directory size can be achieved.
Caching Framework for Big-Data Engines in the Cloud
The present invention is generally directed to a caching framework that provides a common abstraction across one or more big data engines, comprising a cache filesystem including a cache filesystem interface used by applications to access cloud storage through a cache subsystem, the cache filesystem interface in communication with a big data engine extension and a cache manager; the big data engine extension, providing cluster information to the cache filesystem and working with the cache filesystem interface to determine which nodes cache which part of a file; and a cache manager for maintaining metadata about the cache, the metadata comprising the status of blocks for each file. The invention may provide common abstraction across big data engines that does not require changes to the setup of infrastructure or user workloads, allows sharing of cached data and caching only the parts of files that are required, can process columnar format.
Electronic device and method for fabricating the same
This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes a transistor comprising a semiconductor substrate including an active region defined by an isolation layer; and a gate which is formed over the active region and the isolation layer and extends in a first direction to cross the active region, wherein the active region includes a head portion towering over the isolation layer, a body portion disposed under the head portion, and a neck portion which is disposed between the head portion and the body portion and is recessed compared to the head portion and the body portion in the first direction, in a region where the gate and the active region overlap with each other.
Migrating data objects together with their snaps
A technique for performing non-disruptive migration coordinates object migration with snapshot-shipping to migrate both a data object and its snaps from a source to a target. Snapshot-shipping conveys snaps to the target, and an internal snap of the data object serves as a basis for building a migrated version of the data object at the target. As IO requests specifying writes to the data object arrive at the source, a data mirroring operation writes the arriving data both to the data object at the source and to the version thereof at the target. In parallel with the data mirroring operation, a filtering copy operation copies data of the internal snap to the target, but avoids overwriting data mirrored to the target after the internal snap is taken.
Method and apparatus for selecting an interconnect frequency in a computing system
In an embodiment, a processor includes at least one core and an interconnect that couples the at least one core and the cache memory. The interconnect is to operate at an interconnect frequency (f.sub.CL). The processor also includes a power management unit (PMU) including f.sub.CL logic to determine whether to adjust the f.sub.CL responsive to a Bayesian prediction value that is associated with scalability of a workload to be processed by the processor. The Bayesian prediction value may be determined based on one or more activity measures associated with the processor. Other embodiments are described and claimed.
Managing Input/Output Operations for Shingled Magnetic Recording in a Storage System
A system and method for improving the management of data input and output (I/O) operations for Shingled Magnetic Recording (SMR) devices in a network storage system is disclosed. The storage system includes a storage controller that receives a series of write requests for data blocks to be written to non-sequential addresses within a pool of SMR devices. The storage controller writes the data blocks from the series of write requests to a corresponding sequence of data clusters allocated within a first data cache of the storage controller for a thinly provisioned volume of the pool of SMR devices. Upon determining that a current utilization of the first data cache's data storage capacity exceeds a threshold, the sequence of data clusters including the data blocks from the first data cache are transferred to sequential physical addresses within the SMR devices.
CACHING USING AN ADMISSION CONTROL CACHE LAYER
Exemplary methods, apparatuses, and systems receive from a client a request to access data from a client. Whether metadata for the data is stored in a first caching layer is determined. In response to the metadata for the data not being stored in the first caching layer, it is determined if the data is stored in the second caching layer. In response to determining that the data is stored in the second caching layer, the data is retrieved from the second caching layer. In response to determining that the data is not stored in the second caching layer, writing of the data to the second caching layer is bypassed. The retrieved data is sent to the client.
Regulating memory activation rates
Activation rates of memory locations associated with memory addresses are monitored. The activation rates of the memory locations associated with the memory addresses are regulated. The regulating of the activation rates of the memory locations associated with the memory addresses includes selectively updating a cache with the memory addresses based on the activation rates.
Machine learning based cache management
Techniques are disclosed for dynamically managing a cache. Certain techniques include clustering I/O requests into a plurality of clusters by a machine-learning clustering algorithm that collects the I/O requests into clusters of similar I/O requests based on properties of the I/O requests. Further, certain techniques include identifying, for a received I/O request, a cluster stored in the cache. Certain techniques further include loading a set of blocks of the identified cluster into the cache.
Managing caching of extents of tracks in a first cache, second cache and storage
Provided are a computer program product, system, and method for managing caching of extents of tracks in a first cache, second cache and storage device. A determination is made of an eligible track in a first cache eligible for demotion to a second cache, wherein the tracks are stored in extents configured in a storage device, wherein each extent is comprised of a plurality of tracks. A determination is made of an extent including the eligible track and whether second cache caching for the determined extent is enabled or disabled. The eligible track is demoted from the first cache to the second cache in response to determining that the second cache caching for the determined extent is enabled. Selection is made not to demote the eligible track in response to determining that the second cache caching for the determined extent is disabled.