Technologies for addressing individual bits in memory include a device having a memory that includes partitions that each have tiles, in which each tile stores an individual bit. The device also includes circuitry to receive a request to access (e.g., read or write) a sequence of bits in a partition. The request specifies a logical row or column address. A corresponding tile is determined from the logical row or column address and for each bit in the sequence. The corresponding tile is accessed to read or write the bit therein.

A mobile device (100) includes a processing device (140), a random access memory, RAM, (150) and an embedded mass storage device (160). A first interface (IF1) is provided between the processing device (140) and the RAM (150). The first interface (IF1) supports access of the processing device (140) to the RAM (150). The mass storage device (160) includes a controller (170) and a non-volatile flash memory (180). A second interface (IF2) is provided between the controller (170) and the flash memory (180). The second interface (IF2) supports access of the controller (170) to the flash memory (180). A third interface (IF3) is provided between the controller (170) and the processing device (140). The third interface (IF3) supports access of the controller (170) to the RAM (150).

An apparatus is described. The apparatus can include non-volatile memory, an embedded processor, and a memory controller. The memory controller can access data from the byte addressable non-volatile memory using at least one of: a first addressing scheme or a second addressing scheme. The memory controller can provide the data to a host system over a first interface when the data is accessed using the first addressing scheme. The memory controller can provide the data to the embedded processor over a second interface when the data is accessed using the second addressing scheme.

A data storage device includes a memory device including multiple memory blocks corresponding to multiple sub-regions and a memory controller. The memory controller accesses the memory device and updates content of a read count table in response to a read command with at least one designated logical address issued by a host device. Each field of the read count table records a read count associated with one sub-region and the content of the read count table is updated by increasing the read count associated with the sub-region that the designated logical address belongs to. The memory controller selects at least one sub-region to be rearranged according to the content of the read count table and performs a data rearrangement procedure to move data of logical addresses belonging to the selected at least one sub-region to a first memory space of the memory device having continuous physical addresses.

Methods, non-transitory machine readable media, and computing devices that manage resources between multiple hosts coupled to dual-port solid-state disks (SSDs) are disclosed. With this technology, in-core conventional namespace (CNS) and zoned namespace (ZNS) mapping tables are synchronized by a host flash translation layer with on-disk CNS and ZNS mapping tables, respectively. An entry in one of the in-core CNS or ZNS mapping tables is identified based on whether a received storage operation is directed to a CNS or a ZNS of the dual-port SSD. The entry is further identified based on a logical address extracted from the storage operation. The storage operation is serviced using a translation in the identified entry for the logical address, when the storage operation is directed to the CNS, or a zone identifier in the identified entry for a zone of the ZNS, when the storage operation is directed to the ZNS.

According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.

A data storage device utilized for storing a plurality of data includes a memory and a controller. The memory includes a plurality of blocks, and each of the blocks includes a plurality of physical pages. The controller is coupled to the memory. When the data storage device is initiated, or when the data size read by a host is greater than a threshold value, the controller inspects the status of the data stored by the physical pages of the memory.

The present disclosure generally relates to split, non-operational power states for a data storage device. The data storage device can transition between the split, non-operational power states without advertising the transition to the host device. The power state parameters that are advertised to the host device are adjusted such that the host device is guided to the correct power decision based on the advertised power and duration. By splitting the non-operational power states, the data storage device does not incur additional transitional energy costs for short idle durations.

A die read counter and a block read counter are maintained for a specified block of a memory device. An estimated number of read events associated with the specified block is determined based on a value of the block read counter and a value of the die read counter. Responsive to determining that the estimated number of read events satisfies a criterion, a media management operation of one or more pages associated with the specified block is performed.

A data storage device utilized for storing a plurality of data includes a memory and a controller. The memory includes a plurality of blocks, and each of the blocks includes a plurality of physical pages. The controller is coupled to the memory and maps the logical pages to the physical pages of the memory. When the controller detects that a first logical page of the logical pages is a currently-used logical page, it detects whether or not the second logical page which belongs to the last logical page of the first logical page is a currently-used logical page in order to find what is truly the last currently-used logical page.