In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.

Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. In an example apparatus, an input/output (I/O) device can receive signaling that includes a command to write to or read data from an address corresponding to a non-persistent memory device, and can determine where to redirect the request. For example, the I/O device can determine to write or read data to and/or from the non-persistent memory device or the persistent memory device based at least in part on one or more characteristics of the data.

In an implementation, a data storage method comprises obtaining a write request by a processing apparatus, where the write request includes first data to be written. Determining based on at least one of an access feature and a service requirement of the first data, a first category of the first data at a current moment; and indicating the storage apparatus to store the first data in a first type of storage unit. The first category indicates a programming rate requirement of the first data, and the first type is determined based on the first category.

A memory controller according to an embodiment includes a control circuit configured to duplicate and store data received from an external host device. The control circuit is configured to, when a write request specifying first data and a first logical address is received: i) allocate a first physical address corresponding to a first bit to the first logical address, and order a first memory device to write the first data to the first physical address; and ii) allocate a first mirroring physical address corresponding to a second bit to the first physical address, and order a second memory device to write the first data to the first mirroring physical address. A number of reads the first bit is different from a number of reads for the second bit.

A memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a memory cell array having pages. The memory system is configured to execute a first operation method and a second operation method. The memory system includes a control information storage unit in which a first value is set for pages having a write operation speed that is slower than a first speed, and a second value is set for pages having a write operation speed that is equal to or higher than the first speed. The memory system is configured to, at the time of write operation, select the first operation method for a target page having the first value and perform the write operation using the first operation method, and select the second operation method for a target page having the second value and perform the write operation using the second operation method.

A method, computer program product, and computer system for controlling, by a computing device, access to a non-volatile memory using a non-volatile lock as a reader of the non-volatile memory. Metadata (MD) non-volatile memory commits may be throttled until capacity of the non-volatile memory is at a threshold capacity.

A non-volatile memory device, a method of operating the non-volatile memory device, and a memory system including the non-volatile memory device are provided. A non-volatile memory device includes a memory cell array including a plurality of memory cells configured to be each programmed to one state of a plurality of states, a page buffer circuit including a plurality of page buffers configured to each store received data as state data indicating a target state of a corresponding one of the plurality of memory cells, the page buffer circuit being configured to perform a state data reordering operation of changing a first state data order into a second state data order during performance of a program operation on selected memory cells of the plurality of memory cells, and a reordering control circuit configured to control the page buffer circuit to perform the state data reordering operation simultaneously with the program operation.

For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, architectures are introduced for the compression of the soft bit data to reduce the amount of data transferred over the memory's input-output interface. For a memory device with multiple planes of memory cells, the internal global data bus is segmented and a data compression circuit associated with each segment. This allows soft bit data from a cache buffer of a plane using one segment to transfer data between the cache buffer and the associated compression circuit concurrently with transferring data from a cache buffer of another plane using another segment, either for compression or transfer to the input-output interface.

A method for rebuilding data when changing erase block sizes in a storage system is provided. The method includes determining one or more erase blocks to be rebuilt and allocating one or more replacement erase blocks, wherein the one or more erase blocks and the one or more replacement erase blocks have differing erase block sizes. The method includes mapping logical addresses, for the one or more erase blocks, to the one or more replacement erase blocks and rebuilding the one or more erase blocks into the one or more replacement erase blocks, in accordance with the mapping.

A memory system includes a controller and a flash memory including a plurality of first blocks. The controller writes a value having a first number of bits per memory cell to a plurality of second blocks, and writes a value having a second number of bits per memory cell to a plurality of third blocks among the first blocks. The second number is more than the first number. The controller writes data from a host device to the second blocks and transcribes valid data from the second blocks to the third blocks. The controller controls the number of second blocks in the first blocks according to an order of completion of the data writing to one or more third blocks and an amount of valid data stored in each of the one or more third blocks.