G06F2212/7208

System and method of data writes and mapping of data for multiple sub-drives

A system and method is disclosed for managing data in a non-volatile memory. The system may include a non-volatile memory having multiple non-volatile memory sub-drives. A controller of the memory system is configured to route incoming host data to a desired sub-drive, keep data within the same sub-drive as its source during a garbage collection operation, and re-map data between sub-drives, separate from any garbage collection operation, when a sub-drive overflows its designated amount logical address space. The method may include initial data sorting of host writes into sub-drives based on any number of hot/cold sorting functions. In one implementation, the initial host write data sorting may be based on a host list of recently written blocks for each sub-drive and a second write to a logical address encompassed by the list may trigger routing the host write to a hotter sub-drive than the current sub-drive.

MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
20230229791 · 2023-07-20 · ·

According to one embodiment, a memory system includes a nonvolatile memory and a controller. In response to receiving from a host a write request designating a first address for identifying data to be written, the controller encrypts the data with the first address and a first encryption key, and writes the encrypted data to the nonvolatile memory together with the first address. In response to receiving from the host a read request designating a physical address indicative of a physical storage location of the nonvolatile memory, the controller reads both the encrypted data and the first address from the nonvolatile memory on the basis of the physical address, and decrypts the read encrypted data with the first encryption key and the read first address.

SSD with compressed superblock mapping table
11561870 · 2023-01-24 · ·

An improved solid state drive (SSD). The SSD comprising a plurality of non-volatile memory dies, each configured to store at least one block of data associated with one of a plurality of superblocks each containing a plurality of blocks; a volatile memory; and a memory controller. The memory controller configured to store a bit map associated with a first superblock of the plurality of superblocks in the volatile memory, wherein the bit map is configured to indicate whether each of the plurality of blocks is a replacement block, store a block address list in the volatile memory, the block address list is configured to store an address of one or more replacement blocks, and store a replacement block index in the volatile memory associated with the first superblock of the plurality of superblocks, the replacement block index corresponding to the location of an address of a first replacement block of the first superblock in the block address list.

Heterogeneous erase blocks

A method of using flash storage devices with different sized erase blocks is provided. The method includes allocating a plurality of erase blocks of heterogeneous erase block sizes to a RAID stripe, to form a tile pattern having the heterogeneous erase block sizes in the RAID stripe. The method includes writing the RAID stripe across the flash storage devices in accordance with the allocating, and stopping the writing the RAID stripe, responsive to contents of the RAID stripe reaching a threshold.

Budgeting open blocks based on power loss protection

A storage system has zones in solid-state storage memory, with power loss protection. The system identifies portions of data for processes that utilize power loss protection. The system determines to activate or deactivate power loss protection for the portions of data for the processes. The system tracks activation and deactivation of power loss protection in zones in the solid-state storage memory, in accordance with the portions of data having power loss protection activated or deactivated.

Memory sub-systems including memory devices of various latencies and capacities
11704057 · 2023-07-18 · ·

A write request comprising a logical address, a payload, and an indicator reflecting the character of the payload is received from an application. Based on the indicator, a value of a parameter associated with storing the payload on one or more of a plurality of memory devices is identified. The value of the parameter is determined to satisfy a criterion associated with a particular memory device of the plurality of memory devices. The payload is stored on the particular memory device.

SOLID STATE DRIVE MANAGEMENT METHOD AND SOLID STATE DRIVE
20230013322 · 2023-01-19 · ·

A solid state drive management solution is provided, and includes: detecting that a usage status of a first storage space of an SSD meets a preset condition, where the first storage space works in a first mode; and enabling, based on the detection result, the first storage space to work in a second mode to obtain a second storage space, where a quantity of bits that can be stored in a cell in the first storage space is greater than a quantity of bits that can be stored in a cell in the second storage space.

Storage system with multiplane segments and query based cooperative flash management

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

SYSTEMS AND METHODS FOR LOAD BALANCING IN A HETEROGENEOUS MEMORY SYSTEM
20230017824 · 2023-01-19 ·

A system is disclosed. The system may include a processor and a memory connected to the processor. A first storage device may be connected to the processor. The first storage device may include a first storage portion, which may include a memory page. The first storage portion may extend the memory. A second storage device may also be connected to the processor. The second storage device may also include a second storage portion. The second storage portion may also extend the memory. A load balancing daemon may migrate the memory page from the first storage portion of the first storage device to the second storage portion of the second storage device based at least in part on a first update count of the first storage device and a second update count of the second storage device.

SYSTEMS, METHODS, AND DEVICES FOR PAGE RELOCATION FOR GARBAGE COLLECTION
20230019878 · 2023-01-19 ·

A method for page management in a memory system may include allocating a page of a mirror memory, copying a valid page from a block of device memory at a device to the page of the mirror memory, remapping the valid page from the block of device memory to the mirror memory, and modifying the block of device memory. The method may further include copying the valid page from the mirror memory to a free page at the device, and remapping the valid page from the mirror memory to the free page at the device. The remapping may be performed using a memory coherent interface. The method may further include deallocating a portion of the mirror memory associated with the valid page based on copying the valid page from the mirror memory.