A storage system has volatile memory for use as a cache and can extend the available caching space by using a host memory buffer (HMB) in a host. However, because accesses to the HMB involve going through a host interface, there may be latencies in accessing the HMB, To reduce access latencies, the storage system views the volatile memory and the HMB as a two-level cache. In one use case, the storage system decides whether to store a logical-to-physical address table in the volatile memory or in the HMB based on a prediction of the likelihood that the table will be updated. If the likelihood for an update is above a threshold, the table is stored in the volatile memory, thereby eliminating the access latencies that would be encountered if the table needs to be updated and is stored in the HMB.

An example apparatus comprises a controller coupled to a non-volatile memory (NVM) device. The controller may be configured to cause a logical block address (LBA) to be stored in a first logical-to-physical (L2P) data structure in the NVM device and a physical block address (PBA) to be stored in a second L2P data structure in the NVM device The first L2P data structure and the second L2P data structure may have a same size associated therewith.

A storage device includes a nonvolatile memory device that includes a first area, a second area, and a third area, and a controller that receives a write command and first data from a host device, preferentially writes the first data in the first area or the second area rather than the third area when the first data is associated with a turbo write, and writes the first data in the first area, the second area, or the third area when the first data is associated with a normal write. The controller moves second data between the first area, the second area, and the third area based on the policy received from the host device.

Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). A non-volatile memory (NVM) is arranged into multiple garbage collection units (GCUs) each separately erasable and allocatable as a unit. Read circuitry applies read voltages to memory cells in the GCUs to sense a programmed state of the memory cells. Calibration circuitry groups different memory cells from different GCUs into calibration groups that share a selected set of read voltages. A read command queue accumulates pending read commands to transfer data from the NVM to a local read buffer. Read command coalescing circuitry coalesces selected read commands from the queue into a combined command for execution as a single batch command. The combined batch command may include read voltages for use in retrieval of the requested data.

An operating method of a memory controller configured to control a memory device including memory blocks each for storing a plurality of pages is provided. The operating method includes transferring a program command to the memory device based on a write request from a host, updating a valid page bitmap representing validity of a plurality of pages based on valid page information received from the memory device, calculating a fragmentation ratio representing a segmentation degree between at least one valid page and at least one invalid page of a memory block based on the valid page bitmap, determining source blocks among the memory blocks in ascending order of fragmentation ratios, and performing garbage collection on the source blocks.

A logical-to-physical (L2P) data structure and a physical-to-logical (P2L) data structure are maintained. The L2P data structure comprises table entries that map a logical address to a physical address. The P2L data structure comprises data entries that map a physical address to a logical address. The P2L data entries also comprise a data move status, a base address, and a boundary indicator. A move operation is detected, wherein the move operation indicates that data referenced by a logical address is to be moved from a source physical address to a destination physical address. Responsive to detecting the move operation, the data move status associated with the source physical address in the P2L data structure is updated.

A non-volatile memory includes a plurality of physical blocks each including a respective plurality of cells, where each cell is individually capable of storing multiple bits of data. A controller for the non-volatile memory maintains dynamically resizable pools of physical blocks, including at least a low-density pool of physical blocks in which cells are configured to store a fewer number of bits and a high-density pool of physical blocks in which cells are configured to store a greater number of bits. The controller detects an imbalance in utilization between the low-density and high-density pools and, based on detection of the pool imbalance, restricts data placement in the low-density pool, enables garbage collection from the low-density pool back into the low-density pool to compact the low-density pool, and re-enables data placement to the low-density pool based on availability of a threshold number of free physical blocks in the low-density pool.

Devices and techniques for efficient obfuscated logical-to-physical mapping are described herein. For example, activity corresponding to obfuscated regions of an L2P map for a memory device can be tracked. A record of discontinuity between the obfuscated regions and L2P mappings resulting from the activity can be updated. The obfuscated regions can be ordered based on a level of discontinuity from the record of discontinuity. When an idle period is identified, an obfuscated region from the obfuscated regions is selected and refreshed based on the ordering.

Apparatuses and methods for concurrently accessing different memory planes are disclosed herein. An example apparatus may include a controller associated with a queue configured to maintain respective information associated with each of a plurality of memory command and address pairs. The controller is configured to select a group of memory command and address pairs from the plurality of memory command and address pairs based on the information maintained by the queue. The example apparatus further includes a memory configured to receive the group of memory command and address pairs. The memory is configured to concurrently perform memory access operations associated with the group of memory command and address pairs.

An error associated with host data written to a page of a storage area of a memory sub-system is detected. A determination is made that parity data corresponding to the host data is stored in a cache memory of the memory sub-system. A data recovery operation is performed based on the parity data stored in the cache memory.