In some embodiments, a method includes receiving, at a central processing unit (CPU)-based demultiplexer of a CPU, an input video data stream; performing, at the CPU, an accelerator decoding configuration assessment of an accelerator decoding configuration of an accelerator; and based upon the accelerator decoding configuration assessment, dynamically decoding CPU-based demultiplexer output from the CPU-based demultiplexer using a CPU-based decoding unit and an accelerator-based decoding unit. In some embodiments of the method, the accelerator decoding configuration assessment includes performing an accelerator-based decoding unit hardware configuration assessment of the accelerator-based decoding unit and a CPU-based decoding unit software configuration assessment of the CPU-based decoding unit software utilized for the CPU-based decoding unit.

In some embodiments, a computer-implemented method includes receiving, at a security agent of a host central processing unit (CPU), accelerator firmware from flash memory; determining, at the security agent, whether the accelerator firmware includes a critical accelerator firmware component or a non-critical accelerator firmware component; authenticating, at the security agent, the critical accelerator firmware component instantaneously upon a determination that the accelerator firmware is the critical accelerator firmware component, wherein authenticating the critical accelerator firmware component yields an authenticated critical accelerator firmware component; and providing the authenticated critical accelerator firmware component to an accelerator via a sideband bus for execution at the accelerator.

Systems and methods are disclosed for implementing a Non-Volatile Memory Express (NVMe) driver in a computer system. The method involves mapping a memory buffer into a user mode address space to facilitate data transfer with an NVMe device via direct memory access (DMA). Additionally, a first NVMe queue pair, including a submission queue (SQ) and a completion queue (CQ), is mapped into the user mode address space, allowing a user mode component to submit commands to the NVMe device. The method further enables the user mode component to ring a doorbell at the NVMe device. Finally, an NVMe command is processed in kernel mode using a second NVMe queue pair comprising a second SQ and a second CQ.