By assigning a physically continuous memory area to a virtual storage apparatus operated on an OS, the performance of the virtual storage apparatus is secured. A processor operates an OS, and the processor executes a plurality of processes on the OS. The plurality of processes includes a first virtual storage apparatus. The first virtual storage apparatus executes an I/O process, and includes a cache for storing data that is subjected to the I/O process. The processor assigns a resource in a computer to the plurality of processes, and the processor creates area information that indicates physical addresses assigned to the processes in a memory. On the basis of the area information, the processor selects a continuous area, which is a physically continuous area from the memory and assigns the continuous area to the cache.

A storage apparatus accessed by using a memory bus is disclosed. The apparatus includes an interface controller, a storage module, a storage controller, a command register, a status register, and a buffer. In addition, the interface controller can be electrically connected to a memory module interface of a computer system. The interface controller receives an access command for accessing the storage module sent by a CPU. The interface controller writes the access command into the command register, and records a current access status or result by using the status register. The storage controller performs status setting on the status register according to the access command in the command register, and performs a corresponding read/write operation on the storage module.

Direct memory access (DMA) is provided in a computing system that includes a central processing unit (CPU), CPU memory associated with the CPU, a graphics processing unit (GPU), GPU memory associated with the GPU, a storage device capable of direct memory access, and a peer-to-peer host bus to which the other components are electrically coupled, directly or indirectly. For each page of the GPU physical memory, a data structure representing the page of GPU physical memory is generated, a GPU virtual memory space is allocated, the GPU virtual memory space is mapped to a GPU physical memory space. Based on the data structure representing the page of GPU physical memory, the GPU physical memory space is mapped to a CPU virtual address associated with a user-space process. A direct input/output operation on the storage device is initiated using the CPU virtual address, which is mapped to the GPU physical memory, at least a bus address is generated based on the data structure representing the page of GPU physical memory, and a DMA operation is initiated based on the bus address to transfer data between the storage device and the GPU physical memory space through the peer-to-peer host bus without copying the data to the CPU memory.

Disclosed herein are systems, methods, and processes to improve throughput in OpenFabrics and Remote Direct Memory Access (RDMA) computing environments. Data and a header is received. Buffers in which the data and the header are to be written are identified. Placement information for the data and the header is determined based on a size of each buffer, a page-boundary-alignment of the data, and a header alignment of the header. The data and the header are written to the buffer(s) using the placement information. In such computing environments, throughout can be improved by writing data on page boundaries and the header on a header boundary in a second to last buffer.

System and techniques for enhanced electronic navigation maps for a vehicle are described herein. A descriptor set-up message may be received at a network controller interface (NIC). Here, the descriptor set-up message includes an ethernet frame descriptor. The NIC may then use the ethernet frame descriptor to transmit, across a physical interface of the NIC, multiple ethernet frames, each of which use the same ethernet frame descriptor from the set-up message.

A memory management circuit includes a direct memory access (DMA) channel. The DMA channel includes logic configured to receive a buffer of data to be written using DMA. The DMA channel further includes logic to perform bit manipulation in real-time during a DMA write cycle of the first buffer of data.

A network interface device includes a port with protocol circuitry to couple to a host device by a link compliant with a Compute Express Link (CXL) protocol. The network interface device further includes a memory and logic to support emulation of a file system by the host device of at least a portion of the memory, where the link is used for direct memory accesses for requests or responses associated with the emulation of the file system.

According to one general aspect, a method may include receiving a request, from a non-central processor device that is configured to perform a direct memory access, to write data within a memory system at a memory address. The method may also include determining if a cache tag hit is generated, based upon the memory address, by a caching tier of the memory system that is closer, latency-wise, to a central processor than a coherent memory interconnect. The method may further include if the caching tier generated the cache tag hit, injecting the data into the caching tier.

Direct memory access (DMA) is provided in a computing system that includes a central processing unit (CPU), CPU memory associated with the CPU, a graphics processing unit (GPU), GPU memory associated with the GPU, a storage device capable of direct memory access, and a peer-to-peer host bus to which the other components are electrically coupled, directly or indirectly. For each page of the GPU physical memory, a data structure representing the page of GPU physical memory is generated, a GPU virtual memory space is allocated, the GPU virtual memory space is mapped to a GPU physical memory space. Based on the data structure representing the page of GPU physical memory, the GPU physical memory space is mapped to a CPU virtual address associated with a user-space process. A direct input/output operation on the storage device is initiated using the CPU virtual address, which is mapped to the GPU physical memory, at least a bus address is generated based on the data structure representing the page of GPU physical memory, and a DMA operation is initiated based on the bus address to transfer data between the storage device and the GPU physical memory space through the peer-to-peer host bus without copying the data to the CPU memory.

A technique allows for protecting a PCI device controller from a PCI BDF masquerade attack from Ring-0 and Ring-3 malware. The technique may use Virtualization technologies to create guest virtual machines that can use a hypervisor to allocate ACPI information from ACPI tables to a secure VM and using extended page tables (EPT) and VT-d policies to protect the MMIO memory range during illegal runtime events.