A computer booting apparatus includes a computer processor, a computer memory coupled to the computer processor, and a communication port coupled to the computer processor. The computer processor is configurable for operation in a host mode and a device mode. The host mode connects to an external computer processor and an external computer memory via the communication port, checks for a new image file or a revised image file stored in the external computer processor or the external computer memory, and loads the new image file or the revised image file into the computer memory. The device mode boots a device via the communication port using the new image file or the revised image file.

A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.

A network architecture including network storage. The network architecture includes a plurality of streaming arrays, each streaming array including a plurality of compute sleds, wherein each compute sled includes one or more compute nodes. The network architecture includes a PCI Express (PCIe) fabric configured to provide direct access to the network storage from compute nodes of each of the plurality of streaming arrays, the PCIe fabric including a plurality of array-level PCIe switches, each array-level PCIe switch communicatively coupled to compute nodes of compute sleds of a corresponding streaming array and communicatively coupled to the storage server. The network storage is shared by the plurality of streaming arrays.

A data processing system is presented that includes multiple local buses, a host processor, a network interface controller (NIC) for connecting to external storage via a network, one or more reconfigurable processors, and a bus switch. The bus switch couples the multiple local busses, thereby operatively coupling the one or more reconfigurable processors, the host processor, and the NIC. The one or more reconfigurable processors are configured to implement a virtual function that uses a virtual address for a memory access operation. The host processor is configured to implement an application programming interface (API) that translates the virtual address into a physical address, and the NIC uses the physical address to initiate a direct data access operation at the external storage that moves data directly between the one or more reconfigurable processors and the external storage, wherein the data bypasses the host processor.

Traditionally, servers are interconnected inside a data center using regular network cards. It is desired that high-available network-attached storage arrays have the feature of non-disruptive upgrade (NDU) for software and firmware, while one or more applications are still running IO. With the emergence of SmartNICs, there are many functions available now to SmartNIC that may enhance server and entire solution capabilities. Since SmartNIC is a new emerging technology, there are no adequate solutions currently for NDU while running I/O. The present patent document discloses embodiments for upgrading the SmartNIC software without disruption to the host applications. A shared namespace may be implemented inside an emulated NVMe/PCIe device, such as a data processing unit (DPU) or infrastructure processing unit (IPU), such that multiple instances may be enabled to run both old and new target emulation SPDK-based software together using multiple paths to achieve SmartNIC storage NDU.

A system is presented that includes two data processing systems that are coupled via a network, each data processing system including a reconfigurable processor with a reconfigurable processor memory, a host that is coupled to the reconfigurable processor and that includes a host processor and a host memory that is coupled to the host processor, and a network interface controller (NIC) that is operatively coupled to the reconfigurable processor and to the host processor. The reconfigurable processor of one of the data processing systems is configured to implement a virtual function that uses a virtual address for a memory access operation. An application programming interface (API) in the host processor translates the virtual address into a physical address, and the NIC uses the physical address to initiate a direct memory access operation at the reconfigurable processor memory or the host memory of the other data processing system.

Technologies for allocating resources across data centers include a compute device to obtain resource utilization data indicative of a utilization of resources for a managed node to execute a workload. The compute device is also to determine whether a set of resources presently available to the managed node in a data center in which the compute device is located satisfies the resource utilization data. Additionally, the compute device is to allocate, in response to a determination that the set of resources presently available to the managed node does not satisfy the resource utilization data, a supplemental set of resources to the managed node. The supplemental set of resources are located in an off-premises data center that is different from the data center in which the compute device is located. Other embodiments are also described and claimed.

A data processing apparatus includes a power-source controller, a data processing device, a physical-layer section, a communication controller, and a state controller. The power-source controller controls a first power-source setting and a second power-source setting. The second power-source setting causes less electric power consumption than the first power-source setting. The communication controller performs the communication with the data processing device through a predetermined communication path and the physical-layer section under the first power-source setting. The communication controller stops the communication with the data processing device through the communication path and the physical-layer section under the second power-source setting. The state controller maintains the second communication state with respect to the data processing device side of the communication path while electric power supply to the physical-layer section is reduced under the second power-source setting.

A network interface controller (NIC) capable of efficient management of non-idempotent operations is provided. The NIC can be equipped with a network interface, storage management logic block, and an operation management logic block. During operation, the network interface can receive a request for an operation from a remote device. The storage management logic block can store, in a local data structure, outcome of operations executed by the NIC. The operation management logic block can determine whether the NIC has previously executed the operation. If the NIC has previously executed the operation, the operation management logic block can obtain an outcome of the operation from the data structure and generate a response comprising the obtained outcome for responding to the request.

Systems and methods are provided for passing data amongst a plurality of switches having a plurality of links attached between the plurality of switches. At a switch, a plurality of load signals are received from a plurality of neighboring switches. Each of the plurality of load signals are made up of a set of values indicative of a load at each of the plurality of neighboring switches providing the load signal. Each value within the set of values provides an indication for each link of the plurality of links attached thereto as to whether the link is busy or quiet. Based upon the plurality of load signals, an output link for routing a received packet is selected, and the received packet is routed via the selected output link.