Patent classifications
G06F2213/3852
CONNECTION INTERFACE CONVERSION CHIP, CONNECTION INTERFACE CONVERSION DEVICE AND OPERATION METHOD
A connection interface conversion chip, a connection interface conversion device and an operation method are provided. The connection interface conversion chip includes a USB interface circuit, a DP interface circuit, a USB core circuit and a switching circuit. The USB interface circuit is suitable for coupling to a USB connector. The DP interface circuit is suitable for coupling to a DP connector. In a first operation mode, at least one USB signal pair received by the USB connector is transmitted to the USB core circuit through the USB interface circuit. The USB core circuit decodes the USB signal pair and generates DP data. The DP data is transmitted to the DP connector by the DP interface circuit. In a second operation mode, the DP data received by the USB connector is transmitted to the DP connector through the USB interface circuit, the switching circuit and the DP interface circuit.
USE OF HOST BUS ADAPTER TO PROVIDE PROTOCOL FLEXIBILITY IN AUTOMATED TEST EQUIPMENT
An automated test equipment (ATE) system comprises a system controller communicatively coupled to a tester processor, where the system controller is operable to transmit instructions to the tester processor, and where the tester processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The apparatus also comprises an FPGA programmed to support a first protocol communicatively coupled to the tester processor comprising at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing a DUT of the plurality of DUTs. Further, the apparatus comprises a bus adapter comprising a protocol converter module operable to convert signals associated with the first protocol received from the FPGA to signals associated with a second protocol prior to transmitting the signals to the DUT, wherein the DUT communicates using the second protocol.
Bus control circuit, semiconductor integrated circuit, circuit board, information processing device and bus control method
A bus control circuit configured to transfer access commands for performing exclusive access between a first bus specification and a second bus specification by converting from a first exclusive access command applying to the first bus specification which deals with exclusive access, into a second exclusive access command of the second bus specification which doesn't deal with the exclusive access. The circuit includes an exclusive access command conversion circuit for receiving the first exclusive access command, converting the first exclusive access command into the second exclusive access command, and outputting the second exclusive access command; an exclusive access command generation circuit for receiving the second exclusive access command and generate the first exclusive access command; an exclusive access response issuing circuit for issuing exclusive access response information for the second exclusive access command; and an exclusive access response receiving circuit for receiving exclusive access response information for the second exclusive access command.
RELAY DEVICE, RECEIVING DEVICE, AND TRANSMISSION SYSTEM USING SAME
There is a problem that video data cannot be relayed from a transmission device having an HDMI connector to a receiving device having a USB Type-C connector. In order to solve the above problem, each of a receiving device having an HDMI reception function unit and a relay device, such as a conversion cable for relaying video data from a transmission device, is made to have a function of determining the other devices. By performing switching of a terminator or a protection element between valid and invalid or performing signal connection switching based on the determination result of the function unit, the above problem can be solved. In addition, it is also possible to realize reverse insertion connection for reversing the video data transmission direction of the relay device.
USB and thunderbolt optical signal transceiver
Systems and methods to implement a USB and Thunderbolt optical signal transceiver are described. One method includes detecting presence of a USB sideband signal received over an optical communication channel and associated with a USB communication request. Responsive to the detecting, the method may determine that the USB communication request corresponds to a USB communication mode and perform a sideband negotiation. The USB communication mode may be enabled. A specified number of channels associated with the USB communication request may be determined. USB communication may be performed using the specified number of channels over the optical communication channel in the USB communication mode.
REMOTE LOGIN METHOD FOR SERVER SUBSYSTEM AND REMOTE LOGIN SYSTEM
This invention provides a remote login method for a server subsystem comprising: sending a commands from a user terminal to a controller via a network; determining whether the command of the user terminal conforming to a preset format via the controller; executing a sequence port debug firmware when the commands of the user terminal conforming to the preset format; when the executed sequence port debug firmware is executed, enabling a data transmission channel between the controller and the server subsystem via the executed sequence port. In this way, the user terminal can log in the server subsystem remotely through the server controller to manage the server subsystem.
USB and thunderbolt optical signal transceiver
Systems and methods to implement a USB and Thunderbolt optical signal transceiver are described. One method includes detecting presence of a USB sideband signal received over an optical communication channel and associated with a USB communication request. Responsive to the detecting, the method may determine that the USB communication request corresponds to a USB communication mode and perform a sideband negotiation. The USB communication mode may be enabled. A specified number of channels associated with the USB communication request may be determined. USB communication may be performed using the specified number of channels over the optical communication channel in the USB communication mode.
Apparatus and method and computer program product for accessing a memory card
The invention introduces an apparatus for accessing a memory card to at least include a host interface and a processing unit. The processing unit is arranged to operably inspect whether a logical block length utilized in a memory card inserted into a card reader can be supported by a host; and reply to the host with sense data that advises the host not to perform a subsequent write into the memory card through the host interface in response to a request sense command when the logical block length utilized in the memory card cannot be supported by the host.
Techniques of providing serial port in non-legacy system via embedded-system device
In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be an embedded-system device. The apparatus may be an embedded-system device. The embedded-system device emulates a first serial port. The embedded-system device exposes the first serial port to a host of the embedded-system device through a USB connection. The embedded-system device receives first USB packets containing first command or data from the host through the USB connection. The embedded-system device inputs the first command or data to the first serial port.
Secure digital format card having two interfaces to communicate with two processors
A secure digital format card that includes two interfaces to a processor is provided, comprising a housing, and a processor that includes a secure digital input/output (SDIO) interface, a second interface, and further connections different from the interfaces. A first set and second set of pads are located at the housing, a subset of the first set for communicating with the processor via the SDIO interface. A subset of the second set for communicating with the processor via the second interface, and a further subset of the second set for communicating with the processor via the further connections. The processor is configured to: enable the subset of the second set of pads via the second interface when enable data is received via the one or more further connections, from the further subset of the second set of pads.