Patent classifications
G06F2213/3854
Semiconductor device and memory system
A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.
Semiconductor device and memory system
A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8 b/10 b coding for the symbol. The transmission unit transmits the symbol coded by the 8 b/10 b coding unit to the host apparatus.
SEMICONDUCTOR DEVICE AND MEMORY SYSTEM
A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.
Multi-partitioning of memories
Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.
SEMICONDUCTOR DEVICE AND MEMORY SYSTEM
A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.
METHODS AND SYSTEMS FOR FACILITATING JOINT SUBMISSIONS
Methods, systems, and devices for facilitating joint submissions. In an example embodiment, a system may facilitate a joint submission from multiple devices. For example, a primary device may receive data for a joint submission with a peripheral device, and the data may be segmented into sensitive and non-sensitive data.
DEVICE SELF-CALIBRATION AND COMPONENT RESOLUTION
Events generated from a terminal are analyzed and a problem associated with a component peripheral of the terminal is identified. Operations and parameters to the operation are obtained to resolve the problem. The operations and parameters are encoded in a code along with security information. The code is provided to a mobile device. The mobile device provides the code back to the terminal. The terminal verifies the security information from the code and decodes the operations and parameters. The operations with the parameters are processed to resolve the problem on the terminal, and the security information and code are logged for auditing.
SEMICONDUCTOR DEVICE AND MEMORY SYSTEM
A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8 b/10 b coding for the symbol. The transmission unit transmits the symbol coded by the 8 b/10 b coding unit to the host apparatus.
MULTI-PARTITIONING OF MEMORIES
Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.
Methods and systems for facilitating joint submissions
Methods, systems, and devices for facilitating joint submissions. In an example embodiment, a system may facilitate a joint submission from multiple devices. For example, a primary device may receive data for a joint submission with a peripheral device, and the data may be segmented into sensitive and non-sensitive data.