A hot plug method, a host controller, a host, and a PCIe bridge device. The method includes: generating, by a host controller, a first notification packet, where the first notification packet includes hot plug interruption information, and the hot plug interruption information indicates that a first PCIe device is to be hot-plugged; sending, by the host controller, the first notification packet to a host, so that the host performs, according to the first notification packet, a hot plug operation corresponding to the PCIe device; and receiving, by the host controller, a second notification packet sent by the host, and sending the second notification packet to a user equipment controller, to facilitate the user equipment controller to instruct a user to insert or remove the PCIe device, where the second notification packet is for indicating that the hot plug operation corresponding to the PCIe device is completed.

In accordance with embodiments of the present disclosure, an information handling system may include two processor sockets comprising a first processor socket and a second processor socket, a first information handling resource communicatively coupled to the first processor socket, second information handling resource, and a bus exchange switch communicatively coupled to the first processor socket, the second processor socket, and the second information handling resource such that: if the second processor socket is unpopulated, the bus exchange switch creates a first electrically conductive path between the first processor socket and the second information handling resource, and if the second processor socket is populated, the bus exchange switch creates a second electrically conductive path between the first processor socket and the second processor socket and creates a third electrically conductive path between the second processor socket and the second information handling resource.

In accordance with embodiments of the present disclosure, an information handling system may include two processor sockets comprising a first processor socket and a second processor socket, a first information handling resource communicatively coupled to the first processor socket, second information handling resource, and a bus exchange switch communicatively coupled to the first processor socket, the second processor socket, and the second information handling resource such that: if the second processor socket is unpopulated, the bus exchange switch creates a first electrically conductive path between the first processor socket and the second information handling resource, and if the second processor socket is populated, the bus exchange switch creates a second electrically conductive path between the first processor socket and the second processor socket and creates a third electrically conductive path between the second processor socket and the second information handling resource.

An upstream facing port device (UFP device) and a downstream facing port device (DFP device) allow a host device and a USB device to conduct SuperSpeed communication via a non-USB compliant extension medium. In some embodiments, the UFP device helps overcome increased latency by generating synthetic packets to be transmitted to the DFP device in order to pre-fetch more data packets from the USB device than requested by the host device. In some embodiments, the DFP device adjusts service interval timing or caches data packets from the host device in order to compensate for the increased latency. In some embodiments, the DFP device transmits a synthetic acknowledgement packet to the UFP device to indicate a larger amount of free buffer space than is present on the USB device to help overcome the increased latency.

Aspects of the embodiments are directed to systems and methods for performing link training using stored and retrieved equalization parameters obtained from a previous equalization procedure. As part of a link training sequence, links interconnecting an upstream port with a downstream port and with any intervening retimers, can undergo an equalization procedure. The equalization parameter values from each system component, including the upstream port, downstream port, and retimer(s) can be stored in a nonvolatile memory. During a subsequent link training process, the equalization parameter values stored in the nonvolatile memory can be written to registers associated with the upstream port, downstream port, and retimer(s) to be used to operate the interconnecting links. The equalization parameter values can be used instead of performing a new equalization procedure or can be used as a starting point to reduce latency associated with equalization procedures.

Methods and apparatuses relating to circuitry for multilane serial bus communications are described. In an embodiment, an apparatus includes a serial bus controller, upstream serial bus lanes, a single downstream serial bus lane, and a host/device lane controller. The serial bus controller is to send and receive data transmissions to and from serial bus devices. The upstream serial bus lanes correspond to the serial bus devices and are associated with serial port addresses. The host/device lane controller is to receive data transmissions through the upstream serial bus lanes and includes a port address assignment circuit and a multiplexer. The port address assignment circuit is to assign serial port addresses to data transmissions, to be included in data transmissions to identify the upstream serial bus lanes through which the data transmission was received. The multiplexer is to forward data transmissions from upstream serial bus lanes to the downstream serial bus lane.

Embodiments of the present disclosure disclose a method and device for interconnecting terminals, and a storage medium. The method comprises: obtaining, by a first terminal, a user triggered connection request to a second terminal; establishing, by the first terminal, a wireless fidelity connection or a universal serial bus connection with the second terminal; and communicating data, by the first terminal, with the second terminal based on the established connection to implement a data transmission between a first socket port and a second socket port, wherein, the first socket port is a communication port corresponding to a first message center on the first terminal, and the second socket port is a communication port corresponding to a second message center on the second terminal.

A system to regulate the temperature of a Source Port that includes a Port Controller having a first source power capabilities list stored thereon in a non-transitory digital media, the source capabilities list identifying a plurality of first power delivery capabilities that, based on their power requirements, may be negotiated by the Port Controller, a temperature sensor that measures a temperature of the power system and communicates that measured temperature to a comparator. The comparator compares the measured temperature to predefined limit temperatures and when the measured temperature crosses a predefined limit temperature threshold, the first source capabilities list being replaced with a second source capabilities list identifying a plurality of second power capabilities that, based on their power requirements, may be connected to the Source Port.

Methods and apparatuses relating to circuitry for multilane serial bus communications are described. In an embodiment, an apparatus includes a serial bus controller, upstream serial bus lanes, a single downstream serial bus lane, and a host/device lane controller. The serial bus controller is to send and receive data transmissions to and from serial bus devices. The upstream serial bus lanes correspond to the serial bus devices and are associated with serial port addresses. The host/device lane controller is to receive data transmissions through the upstream serial bus lanes and includes a port address assignment circuit and a multiplexer. The port address assignment circuit is to assign serial port addresses to data transmissions, to be included in data transmissions to identify the upstream serial bus lanes through which the data transmission was received. The multiplexer is to forward data transmissions from upstream serial bus lanes to the downstream serial bus lane.

A hot plug method, a host controller, a host, and a PCIe bridge device. The method includes: generating, by a host controller, a first notification packet, where the first notification packet includes hot plug interruption information, and the hot plug interruption information indicates that a first PCIe device is to be hot-plugged; sending, by the host controller, the first notification packet to a host, so that the host performs, according to the first notification packet, a hot plug operation corresponding to the PCIe device; and receiving, by the host controller, a second notification packet sent by the host, and sending the second notification packet to a user equipment controller, to facilitate the user equipment controller to instruct a user to insert or remove the PCIe device, where the second notification packet is for indicating that the hot plug operation corresponding to the PCIe device is completed.