An electricity metering circuit for a matrix operation circuit, having a circuit input for an electrical input current that is an output current of the matrix operation circuit. The electricity metering circuit is set up to provide a ground potential at the circuit input, to integrate the input current at the circuit input over time, to store a storage charge that is increased up to a predetermined maximum storage charge in accordance with a proportionality constant, proportionally to the integrated input current, to quantify the integrated input current in a charge unit, the charge unit corresponding to the maximum storage charge taking into account the proportionality constant, and to determine the integrated input current rounded down to the nearest integer charge unit as a count sum.

A semiconductor device with high arithmetic performance is provided. The semiconductor device employs the translinear principle, and the semiconductor device includes first to tenth transistors each including a metal oxide in a channel formation region and a first capacitor. A first terminal of the first transistor is electrically connected to a first terminal of the second transistor, a first terminal of the third transistor is electrically connected to a second terminal of the second transistor and a gate of the second transistor through the first capacitor. The second terminal of the second transistor is electrically connected to first terminals of the fourth and the seventh transistors and gates of the fifth and the eighth transistors. A gate of the seventh transistor is electrically connected to first terminals of the fifth and the sixth transistors, and a gate of the tenth transistor is electrically connected to first terminals of the eighth and the ninth transistors.

A multiplier has a pair of charge reservoirs. The pair of charge reservoirs are connected in series. A first charge movement device induces charge movement to or from the pair of charge reservoirs at a same rate. A second charge movement device induces charge movement to or from one of the pair of reservoirs, the rate of charge movement programmed to one of add or remove charges at a rate proportional to the first charge movement device. The first charge movement device loads a first charge into a first of the pair of charge reservoirs during a first cycle. The first charge movement device and the second charge movement device remove charges at a proportional rate from the pair of charge reservoirs during a second cycle until the first of the pair of charge reservoirs is depleted of the first charge. The second charge reservoir thereafter holding the multiplied result.

A radio frequency (RF) summer circuit having a characteristic impedance Z.sub.0 comprises first and second ports coupled by first and second resistances, respectively, to a junction. The circuit further comprises a series combination of a third resistance and a switch movable between open and closed positions and an amplifier having input and output terminals and operable in an off state and an on state wherein the series combination is coupled across the input and output terminals of the amplifier between the junction and a third port. The first resistance, second resistance, and the third resistance are all substantially equal to Z.sub.0/3. Further, when the switch is moved to the closed position and the amplifier is switched to the off state a passive mode of operation is implemented and when the switch is moved to the open position and the amplifier is switched to the on state an active mode of operation is implemented. The RF summer circuit develops a summed signal at the third port equal to a sum of signals at the first and second ports modified by one of first and second gain values.

An arithmetic apparatus includes input lines and multiply-accumulate devices. An electrical signal for an input value is input into each of the input lines within a predetermined input period. Multiplication units include a positive weight multiplication unit that generates a positive weight charge for a product value obtained by multiplying the input value by a positive weight value and/or a negative weight multiplication unit that generates a negative weight charge for a product value obtained by multiplying the input value by a negative weight value. They are configured such that a positive weight ratio that is a ratio of a sum total of the positive weight values to a sum total of absolute values of the weight values is any ratio of 0% to 100%. An output unit of the multiply-accumulate device accumulates the generated weight charges to output a multiply-accumulate signal representing a sum of the product values.

An arithmetic apparatus includes input lines and multiply-accumulate devices. An electrical signal for an input value is input into each of the input lines within a predetermined input period. Multiplication units include a positive weight multiplication unit that generates a positive weight charge for a product value obtained by multiplying the input value by a positive weight value and/or a negative weight multiplication unit that generates a negative weight charge for a product value obtained by multiplying the input value by a negative weight value. They are configured such that a positive weight ratio that is a ratio of a sum total of the positive weight values to a sum total of absolute values of the weight values is any ratio of 0% to 100%. An output unit of the multiply-accumulate device accumulates the generated weight charges to output a multiply-accumulate signal representing a sum of the product values.

An arithmetic apparatus includes input lines and multiply-accumulate devices. An electrical signal for an input value is input into each of the input lines within a predetermined input period. Multiplication units include a positive weight multiplication unit that generates a positive weight charge for a product value obtained by multiplying the input value by a positive weight value and/or a negative weight multiplication unit that generates a negative weight charge for a product value obtained by multiplying the input value by a negative weight value. They are configured such that a positive weight ratio that is a ratio of a sum total of the positive weight values to a sum total of absolute values of the weight values is any ratio of 0% to 100%. An output unit of the multiply-accumulate device accumulates the generated weight charges to output a multiply-accumulate signal representing a sum of the product values.

An arithmetic apparatus includes input lines and multiply-accumulate devices. An electrical signal for an input value is input into each of the input lines within a predetermined input period. Multiplication units include a positive weight multiplication unit that generates a positive weight charge for a product value obtained by multiplying the input value by a positive weight value and/or a negative weight multiplication unit that generates a negative weight charge for a product value obtained by multiplying the input value by a negative weight value. They are configured such that a positive weight ratio that is a ratio of a sum total of the positive weight values to a sum total of absolute values of the weight values is any ratio of 0% to 100%. An output unit of the multiply-accumulate device accumulates the generated weight charges to output a multiply-accumulate signal representing a sum of the product values.

A system for evaluating a multiply and add expression. The system comprises an encoder for encoding variables of the multiply and add expression on a time domain signal divided into a plurality of time slots and comprising a first and second impulse on a first and second time slot. The system further comprises an integrator unit operable to receive the time domain signal on a time slot by time slot basis. The integrator unit is operable, to accumulate, on a time-slot-by-time-slot basis, an amplitude value corresponding to a running total of the sum of the amplitude of the impulse signals received, and accumulate, on a time-slot-by-time-slot basis, the accumulated amplitude value. The integrator unit is thereby operable to generate, after receipt of the time domain signal, a value which corresponds to the result of the multiply and add expression.

A system for evaluating a multiply and add expression. The system comprises an encoder for encoding variables of the multiply and add expression on a time domain signal divided into a plurality of time slots and comprising a first and second impulse on a first and second time slot. The system further comprises an integrator unit operable to receive the time domain signal on a time slot by time slot basis. The integrator unit is operable, to accumulate, on a time-slot-by-time-slot basis, an amplitude value corresponding to a running total of the sum of the amplitude of the impulse signals received, and accumulate, on a time-slot-by-time-slot basis, the accumulated amplitude value. The integrator unit is thereby operable to generate, after receipt of the time domain signal, a value which corresponds to the result of the multiply and add expression.