G06G7/20

Device for emulating a bimetallic strip, and device for protecting an electrical line from over-currents
11456591 · 2022-09-27 · ·

An emulating device for emulating a bimetallic strip, the emulating device comprising a current sensor capable of measuring a line current (I.sub.P) flowing through the emulating device, the emulating device being capable of providing a value representative of a cumulative thermal state over time t, which value is referred to as cumulative thermal state, by recursively adding a value representative of an initial thermal state, which value is referred to as initial thermal state, and a value representative of a present thermal state, which value is referred to as present thermal state, which is determined on the basis of the line current (I.sub.P).

DEVICE FOR EMULATING A BIMETALLIC STRIP, AND DEVICE FOR PROTECTING AN ELECTRICAL LINE FROM OVER-CURRENTS
20210273444 · 2021-09-02 ·

The invention relates to an emulating device (EMU) for emulating a bimetallic strip, the emulating device (EMU) comprising a current sensor (CC) capable of measuring a line current (I.sub.P) flowing through the emulating device (EMU), the emulating device (EMU) being capable of providing a value representative of a cumulative thermal state (E.sub.th_n) over time t, which value is referred to as cumulative thermal state (E.sub.th_n), by recursively adding a value representative of an initial thermal state (E.sub.th_i), which value is referred to as initial thermal state (E.sub.th_i), and a value representative of a present thermal state (E.sub.th_on, E.sub.th_off), which value is referred to as present thermal state (E.sub.th_on, E.sub.th_off), which is determined on the basis of the line current (I.sub.P).

RF square-law circuit

A circuit includes a first transistor that conducts a first current responsive to a DC bias voltage and an RF signal. A second transistor conducts a second current responsive to the DC bias voltage. The first current and the second current are mirrored through a pair of current mirrors coupled together through a low-pass filter to filter the envelope of the RF signal.

RF square-law circuit

A circuit includes a first transistor that conducts a first current responsive to a DC bias voltage and an RF signal. A second transistor conducts a second current responsive to the DC bias voltage. The first current and the second current are mirrored through a pair of current mirrors coupled together through a low-pass filter to filter the envelope of the RF signal.

Power detector calibration in integrated circuits

A system and a method for calibrating an output signal of an antenna is disclosed. In one aspect, an apparatus includes a first digital adder configured to generate a gain offset by at least adding gain calibration data from non-volatile memory and gain command data from static memory. The apparatus further includes an amplitude gain circuit configured to modify, based at least in part on the gain offset, an amplitude of a first output signal of a first antenna. The modified amplitude of the first output signal is provided to enable pre-calibration of the first output signal. The apparatus further includes a power detector configured to measure an output power of the first output signal. The apparatus further includes at least one processor configured to generate a difference between the measured and expected output power, and adjust gain command data in response to the generated difference.

Power detector calibration in integrated circuits

A system and a method for calibrating an output signal of an antenna is disclosed. In one aspect, an apparatus includes a first digital adder configured to generate a gain offset by at least adding gain calibration data from non-volatile memory and gain command data from static memory. The apparatus further includes an amplitude gain circuit configured to modify, based at least in part on the gain offset, an amplitude of a first output signal of a first antenna. The modified amplitude of the first output signal is provided to enable pre-calibration of the first output signal. The apparatus further includes a power detector configured to measure an output power of the first output signal. The apparatus further includes at least one processor configured to generate a difference between the measured and expected output power, and adjust gain command data in response to the generated difference.

RF SQUARE-LAW CIRCUIT
20200073428 · 2020-03-05 ·

A circuit includes a first transistor that conducts a first current responsive to a DC bias voltage and an RF signal. A second transistor conducts a second current responsive to the DC bias voltage. The first current and the second current are mirrored through a pair of current mirrors coupled together through a low-pass filter to filter the envelope of the RF signal.

POWER DETECTOR CALIBRATION IN INTEGRATED CIRCUITS

A system and a method for calibrating an output signal of an antenna is disclosed. In one aspect, an apparatus includes a first digital adder configured to generate a gain offset by at least adding gain calibration data from non-volatile memory and gain command data from static memory. The apparatus further includes an amplitude gain circuit configured to modify, based at least in part on the gain offset, an amplitude of a first output signal of a first antenna. The modified amplitude of the first output signal is provided to enable pre-calibration of the first output signal. The apparatus further includes a power detector configured to measure an output power of the first output signal. The apparatus further includes at least one processor configured to generate a difference between the measured and expected output power, and adjust gain command data in response to the generated difference.

POWER DETECTOR CALIBRATION IN INTEGRATED CIRCUITS

A system and a method for calibrating an output signal of an antenna is disclosed. In one aspect, an apparatus includes a first digital adder configured to generate a gain offset by at least adding gain calibration data from non-volatile memory and gain command data from static memory. The apparatus further includes an amplitude gain circuit configured to modify, based at least in part on the gain offset, an amplitude of a first output signal of a first antenna. The modified amplitude of the first output signal is provided to enable pre-calibration of the first output signal. The apparatus further includes a power detector configured to measure an output power of the first output signal. The apparatus further includes at least one processor configured to generate a difference between the measured and expected output power, and adjust gain command data in response to the generated difference.

SYSTEMS AND METHODS FOR MULTI-TIER CENTROID CALCULATION

Described herein are systems and methods that determines a centroid of a waveform in a high noise environment. In one embodiment, the method may include determining a damping threshold and a noise-exclusion threshold for a waveform that define a three tier dynamic range for the waveform comprising a noise-exclusion region, damping region and a full region. The noise-exclusion threshold may be less than the damping threshold. Weights for each of the mass scalars may be determined based on the three tier dynamic range. The centroid may be determined based on the determined weights and their corresponding position vectors.