Methods for solving systems of linear equations via utilization of a vector matrix multiplication accelerator are provided. In one aspect, a method includes receiving, from a controller and by the vector matrix multiplication accelerator, an augmented coefficient matrix. The method also comprises implementing Gaussian Elimination using the vector matrix multiplication accelerator by: monitoring, by a register in at least one swap operation, a row order of the augmented coefficient matrix when a first row is swapped with a second row of the augmented coefficient matrix, delivering, by the controller in at least one multiply operation, an analog voltage to a desired row of the augmented coefficient matrix to produce a multiplication result vector, and adding, in at least one add operation, the first row to another desired row of the augmented coefficient matrix to produce an add result vector. Systems and circuits are also provided.

Methods for solving systems of linear equations via utilization of a vector matrix multiplication accelerator are provided. In one aspect, a method includes receiving, from a controller and by the vector matrix multiplication accelerator, an augmented coefficient matrix. The method also comprises implementing Gaussian Elimination using the vector matrix multiplication accelerator by: monitoring, by a register in at least one swap operation, a row order of the augmented coefficient matrix when a first row is swapped with a second row of the augmented coefficient matrix, delivering, by the controller in at least one multiply operation, an analog voltage to a desired row of the augmented coefficient matrix to produce a multiplication result vector, and adding, in at least one add operation, the first row to another desired row of the augmented coefficient matrix to produce an add result vector. Systems and circuits are also provided.

Methods for solving systems of linear equations via utilization of a vector matrix multiplication accelerator are provided. In one aspect, a method includes receiving, from a controller and by the vector matrix multiplication accelerator, an augmented coefficient matrix. The method also comprises implementing Gaussian Elimination using the vector matrix multiplication accelerator by: monitoring, by a register in at least one swap operation, a row order of the augmented coefficient matrix when a first row is swapped with a second row of the augmented coefficient matrix, delivering, by the controller in at least one multiply operation, an analog voltage to a desired row of the augmented coefficient matrix to produce a multiplication result vector, and adding, in at least one add operation, the first row to another desired row of the augmented coefficient matrix to produce an add result vector. Systems and circuits are also provided.

An analog circuit for solving optimization algorithms comprises three voltage controlled current sources and three capacitors, operatively coupled in parallel to the three voltage controlled current sources, respectively. The circuit further comprises a first inductor, operatively coupled in series between a first pair of the capacitors and the voltage controller current sources and a second pair of the capacitors and the voltage controller current sources. The circuit further comprises a second inductor, operatively coupled in series between the second pair of the capacitors and the voltage controller current sources and a third pair of the capacitors and the voltage controller current sources.

An analog circuit for solving optimization algorithms comprises three voltage controlled current sources and three capacitors, operatively coupled in parallel to the three voltage controlled current sources, respectively. The circuit further comprises a first inductor, operatively coupled in series between a first pair of the capacitors and the voltage controller current sources and a second pair of the capacitors and the voltage controller current sources. The circuit further comprises a second inductor, operatively coupled in series between the second pair of the capacitors and the voltage controller current sources and a third pair of the capacitors and the voltage controller current sources.

Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. This Abstract is not intended to limit the scope of the claims.

Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. This Abstract is not intended to limit the scope of the claims.

An NP-processor is provided that is based on a computing environment consisting of a finite set of multiple-element triggers that are interconnected by common elements. The NP-processor has interference relations between the computing environment elements. Negative feedback is introduced and is intended for isolating an active state, which is the solution to the problem, from an exponential number of modes of oscillation in the computing environment.

An NP-processor is provided that is based on a computing environment consisting of a finite set of multiple-element triggers that are interconnected by common elements. The NP-processor has interference relations between the computing environment elements. Negative feedback is introduced and is intended for isolating an active state, which is the solution to the problem, from an exponential number of modes of oscillation in the computing environment.

According to one embodiment, a cross-correlator comprises a plurality of analog front ends (AFEs), a cross-correlation circuit and a data serializer. Each of the AFEs comprises a variable gain amplifier (VGA) and a corresponding analog-to-digital converter (ADC) in which the VGA receives and modifies a unique analog signal associates with a measured analog radio frequency (RF) signal and the ADC produces digital data associated with the modified analog signal. Communicatively coupled to the AFEs, the cross-correlation circuit performs a cross-correlation operation on the digital data produced from different measured analog RF signals. The data serializer is communicatively coupled to the summing and cross-correlating matrix and continuously outputs a prescribed amount of the correlated digital data.