An image data encoding device includes a data block generating unit configured to split image data into a plurality of data blocks, and a compressing unit configured to generate compressed data with respect to each of the plurality of data blocks, the compressed data including position information regarding positions of first pixels each having a gray scale value equal to a reference gray scale value, and difference values between the reference gray scale value and gray scale values of second pixels, which are different from the reference gray scale value.

An image data encoding device includes a data block generating unit configured to split image data into a plurality of data blocks, and a compressing unit configured to generate compressed data with respect to each of the plurality of data blocks, the compressed data including position information regarding positions of first pixels each having a gray scale value equal to a reference gray scale value, and difference values between the reference gray scale value and gray scale values of second pixels, which are different from the reference gray scale value.

A vehicular display device includes: a display means; a control means for controlling the display of the display means; a non-volatile memory for storing at least an operation program for the control means or image data to be displayed on the display means; and a third connection terminal that can be connected with either a first connection terminal or a second connection terminal having different terminal arrangements. The vehicular display device, housed in an instrument panel of a vehicle, is provided with an external device that communicates with the control means by connecting the first connection terminal or the second connection terminal to the third connection terminal, wherein the control means determines whether over-writing of the non-volatile memory should be allowed in accordance with the type of the connection terminal connected to the third connection terminal.

A vehicular display device includes: a display means; a control means for controlling the display of the display means; a non-volatile memory for storing at least an operation program for the control means or image data to be displayed on the display means; and a third connection terminal that can be connected with either a first connection terminal or a second connection terminal having different terminal arrangements. The vehicular display device, housed in an instrument panel of a vehicle, is provided with an external device that communicates with the control means by connecting the first connection terminal or the second connection terminal to the third connection terminal, wherein the control means determines whether over-writing of the non-volatile memory should be allowed in accordance with the type of the connection terminal connected to the third connection terminal.

The present disclosure provides a device, in particular a multifocal display device. The device includes: a display element configured to generate an image; and a controller configured to control the display element according to at least a first bit sequence provided over a first determined time period and a second bit sequence provided over a second determined time period, in order to generate the image with one or more colors, the bit sequences including for each color a number of bits of different significance. Moreover, the device is configured to generate the first bit sequence from an original bit sequence based on discarding at least one bit of a color and to generate the second bit sequence from the original bit sequence based on discarding at least one other bit of the color.

The present disclosure provides a device, in particular a multifocal display device. The device includes: a display element configured to generate an image; and a controller configured to control the display element according to at least a first bit sequence provided over a first determined time period and a second bit sequence provided over a second determined time period, in order to generate the image with one or more colors, the bit sequences including for each color a number of bits of different significance. Moreover, the device is configured to generate the first bit sequence from an original bit sequence based on discarding at least one bit of a color and to generate the second bit sequence from the original bit sequence based on discarding at least one other bit of the color.

A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.

A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.

To provide an active matrix display device in which power consumption of a signal line driver circuit can be suppressed, so that power consumption of the entire memory can be suppressed. A plurality of memory circuits which can write data of a video signal input to a pixel in one line period and can hold the data are provided in a signal line driver circuit of a display device. Then, the data held in each memory circuit is input to a pixel of a corresponding line as a video signal. By providing two or more memory circuits in a driver circuit, pieces of data of video signals corresponding to two or more line periods can be concurrently held in the memory circuits.

To provide an active matrix display device in which power consumption of a signal line driver circuit can be suppressed, so that power consumption of the entire memory can be suppressed. A plurality of memory circuits which can write data of a video signal input to a pixel in one line period and can hold the data are provided in a signal line driver circuit of a display device. Then, the data held in each memory circuit is input to a pixel of a corresponding line as a video signal. By providing two or more memory circuits in a driver circuit, pieces of data of video signals corresponding to two or more line periods can be concurrently held in the memory circuits.