A display driving module includes a gate driving circuit, a plurality of data lines and a data driving circuit. The pixel circuits in odd-numbered rows and one column are electrically connected to a data line, and the pixel circuits in even-numbered rows and the one column are electrically connected to another data line. The data driving circuit includes a data driver and a multiplexing circuit, the multiplexing circuit includes a first multiplexing sub-circuit and a second multiplexing sub-circuit. The gate driving circuit includes a plurality of levels of shift register units, and an n.sup.th-level shift register unit is electrically connected to the pixel circuits in a (2n−1).sup.th row and a (2n).sup.th row, and configured to apply a same gate driving signal to the pixel circuits in the (2n−1).sup.th row and the (2n).sup.th row, where n is a positive integer.

A second display region has a lower pixel density than a first display region. A third metal layer is located upper than a first metal layer and a second metal layer. The occupancy of the third metal layer in the second display region is lower than the occupancy in the first display region. In a pixel unit, the first metal layer includes a first electrode region to control an amount of electric current in a driving transistor, the second metal layer includes a second electrode region and a third electrode region to supply current to the driving transistor, and the third metal layer includes a main region to form a capacitor included in a capacitive element to store a control voltage for the driving transistor, and an island region surrounded by the main region with a gap and interconnected with a lower electrode region by a via region.

According to an embodiment, an electronic device may include an illuminance sensor including a first modulator obtaining a first signal for first illuminance values during a first integration time and a second modulator obtaining a second signal for second illuminance values during a second integration time, and a processor. The processor may be configured to calculate the first illuminance values and the second illuminance values based on the first and second signals, determine that an ambient light source is a flickering light source based on the second illuminance values, if obtaining display parameter information associated with an image output through the display, compensate for the first illuminance values based on the display parameter information and adjust a brightness value of the display based on the compensated first illuminance values, and if failing to obtain the display parameter information, adjust the brightness value of the display based on the second illuminance values.

A display apparatus includes a display panel including: a pixel array in which pixels including a plurality of light-emitting elements are arranged in a plurality of row lines and sub-pixel circuits provided for each of the plurality of light-emitting elements and providing a driving current to the light-emitting elements. The display apparatus also includes a drive unit is configured to: set image data voltages to the sub-pixel circuits of the display panel in a row line order during a data setting period for each row line; and drive the sub-pixel circuits to provide the driving current to the light-emitting elements of the pixel array in the row line order based on a sweep signal sweeping from a first voltage to a second voltage and the set image data voltages during a light-emitting period for each row line.

In a first output mode, a signal in which a data pulse having a positive polarity voltage value appears in a predetermined cycle is output as a positive polarity gradation data signal, and a signal in which a data pulse having a negative polarity voltage value appears in the predetermined cycle with a phase different from the positive polarity gradation data signal is output as a negative polarity gradation data signal. In a second output mode, the above positive polarity gradation data signal is generated, and a signal in which a data pulse having a negative polarity voltage value appears in the predetermined cycle with the same phase as the positive polarity gradation data signal is output as the negative polarity gradation data signal. The first and second output modes are alternatively executed, and the output mode is switched within a predetermined period at intervals of the predetermined period.

There are provided display controllers and driving methods related to those described in US Published Patent Application No. 2013/0194250. These include (a) a display controller having an update buffer, means for removing from the update buffer pixels not requiring updating, and means to ensure that pixels having certain special states are not removed from the update buffer; (b) a method of driving a bistable display wherein, in a pixel undergoing a white-to-white transition and lying adjacent another pixel undergoing a visible transition, there is applied to the pixel one or more balanced pulse pairs and at least one top-off pulse; (c) a method of driving a bistable display by overlaying a non-rectangular item over a pre-existing image content and then removing the item, where only pixels in the region of the item perform transitions (including self-transitions); and (d) a method of driving a bistable display in which a proportion of background pixels not undergoing an optical change are subjected to a refresh pulse to correct optical state drift.

In examples, an electronic device comprises a camera and a display having a transparent area aligned with the camera. The display comprises a first line corresponding to a pixel row or column of the display, the first line extending from a first end of the display to the transparent area. The display comprises a second line corresponding to the pixel row or column and extending from a second end of the display to the transparent area, the first and second lines separated by a gap. The electronic device includes a controller coupled to the display, the controller to drive the first and second lines consecutively.

The present application discloses a cross voltage compensation method for a display panel, a display panel and a display device. The cross voltage compensation method includes steps of transmitting a preset voltage signal to in-plane data lines after scan of scanning lines of a last row of a current frame is completed and before scanning lines of a first row of a next frame are started, keeping all the scanning lines at a close state while transmitting the preset voltage signal to in-plane data lines, and keeping all the scanning lines at a close state after scan of scanning lines of a last row of a current frame is completed and before scanning lines of a first row of a next frame are started, that is, V-blank time.

According to one embodiment, a display device comprises a display panel, first and second driver chips. The display panel includes first and second edge portions, a display area between the first and second edge portions in a first direction, first signal lines extending to the display area, and second signal lines extending to the display area. The first driver chip is connected to the first edge portion to supply video signals to the first signal lines. The second driver chip is connected to the second edge portion to supply video signals to the second signal lines. Number N of the first signal lines and number M of the second signal lines are alternately arranged in a second direction.

Embodiments of the disclosed subject matter provide a device that includes an organic light emitting device (OLED), and a drive circuit to control the operation of the OLED, comprising a response time accelerator thin film transistor (TFT) configured to short or reverse bias the OLED for a predetermined period of time during a frame time. Other embodiments include an OLED having a plurality of sub-pixels, where one or more of sub-pixels configured to emit light of at least a first color comprises a first emissive area and a second emissive area that are independently controllable, where the first emissive area is larger than the second emissive area. The controller is configured to control the second emissive area to have (i) a higher brightness, and/or (ii) a higher current density than the first emissive area for a first sub-pixel luminance level that is less than a maximum luminance.