G09G2320/0247

Method to reduce diffraction artifacts in a waveguide display and display using the same

A system is provided. The system includes a waveguide configured to guide an image light to propagate inside the waveguide. The system also includes a plurality of diffractive components coupled to the waveguide and switchable between operating in a diffraction state to direct the image light from the waveguide to an eye-box of the system, and operating in a non-diffraction state to transmit a light from a real-world environment to the eye-box. The system further includes a controller coupled with the plurality of diffractive components and configured to switch each of the plurality of diffractive components between operating in the diffraction state during a virtual-world subframe of a display frame and operating in the non-diffraction state during a real-world subframe of the display frame.

DISPLAY PANEL AND DISPLAY DEVICE
20230230547 · 2023-07-20 ·

A display panel and a display device are provided. The display panel includes pixel circuits. Each pixel circuit includes a driving transistor, a data writing circuit, a light-emitting control circuit, a threshold compensation circuit and a bias adjustment circuit. The driving transistor includes a gate electrically connected to a first node, a first terminal electrically connected to a second node, and a second terminal electrically connected to the third node, and is configured to generate a driving current. The third node is connected to a light-emitting element through the light-emitting control circuit. The bias adjustment circuit is configured to provide a signal of a bias adjustment signal terminal to the second node under control of a signal of a first scanning signal terminal in such a manner that a bias state of the driving transistor is adjusted.

DISPLAY APPARATUS
20230230537 · 2023-07-20 ·

A display apparatus includes a display panel, a gate driver, a data driver and an emission driver. The display panel includes a pixel. The gate driver is configured to provide a gate signal to the pixel. The data driver is configured to provide a data voltage to the pixel. The emission driver is configured to provide an emission signal to the pixel. The pixel includes a light emitting element, a driving switching element and a bias switching element. The driving switching element is configured to apply a driving current to the light emitting element. The bias switching element is configured to provide a bias voltage to an input electrode of the driving switching element. A frequency of a bias gate signal applied to a control electrode of the bias switching element is greater than a frequency of a data write gate signal applied to the pixel.

Display device

A display device includes: a pixel part to display an image and including pixels receiving a reference voltage; a controller to determine a value of the reference voltage based on a load of the entire pixel part, and to control a grayscale range of image data according to a location in the pixel part based on the reference voltage; a data driver to supply data voltages to the pixel part through data lines based on grayscale ranges adjusted for each location in the pixel part; and a scan driver to supply a scan signal to the pixels through scan lines.

Electronic device and method for predicting residual image of display and compensating for residual image of the display

An electronic device and method are disclosed. The electronic device includes a housing, a flexible display having a variable display area including: a visible first region, and a second region that is stowable/extendable, a display driver integrated circuit (DDI), and a processor. The processor implements the method, including: when the housing is disposed in a first state in which the second region is stowed, control the flexible display to display a user interface (UI) screen through the first region based on a first driving frequency and a first light emission frequency, control the flexible display to display a compensation image through the second region based on a second driving frequency and a second light emission frequency, wherein the second driving frequency is equal to or less than the first driving frequency, and the second light emission frequency is less than the first light emission frequency.

DATA TRANSMISSION/RECEPTION SYSTEM AND DATA TRANSMISSION/RECEPTION METHOD OF DATA DRIVING DEVICE AND DATA PROCESSING DEVICE

The present disclosure relates to a data transmission and reception method of a data driving device and a data processing device as well as a data transmission and reception system, and more particularly, to a method and a system in which the data driving device receives an initial configuration value from the data processing device, stores the initial configuration value as a configuration restoration value, and rapidly restore an environment for a high-speed communication by using the stored configuration restoration value when a link between the data processing device and the data driving device is lost so as to reduce a time for restoration.

DISPLAY MODULE AND METHOD FOR MANUFACTURING SAME

A display module and a method for manufacturing the same are provided. The display module manufacturing method includes: forming a semiconductor pattern on a substrate; forming a first insulating layer covering the semiconductor pattern on the substrate; forming a gate electrode on a region of the first insulating layer corresponding to a gate region of the semiconductor pattern; forming a second insulating layer covering the gate electrode on the first insulating layer; forming a first hole passing through the first insulating layer and the second insulating layer to expose a drain region of the semiconductor pattern and forming a second hole passing through the first insulating layer and the second insulating layer to expose a source region of the semiconductor pattern; and forming a first barrier pattern on the drain region in the first hole and a second barrier pattern on the source region in the second hole, and forming a drain electrode on the first barrier pattern and a source electrode on the second barrier pattern.

Display panel and display device

A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module. The driving module includes a driving transistor, and is configured to provide a driving current for the light-emitting element. The pixel circuit includes a control terminal configured to receive a first light-emitting control signal, the first light-emitting control signal is an effective pulse, and the driving module corresponding to the control terminal is turned on during the effective pulse. A time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage, an operating state of the pixel circuit includes a first mode and a second mode, a time length of the non-light-emitting stage in the first mode is L1, and a time length of the non-light-emitting stage in the second mode is L2, where L1>L2.

Sub-pixel rendering method for display panel
11705052 · 2023-07-18 · ·

The present application relates to a sub-pixel rendering method for a display panel, which determines sampling locations according to arrangement locations of the sub-pixels, converts an input image according to a human vision model for correspondingly generating an adjustment luminance data, and samples a plurality of adjustment luminance value of the adjustment luminance data according to the sampling locations. Thereby, corresponded target grayscale data is generated. Thus, the input image is prevented from distortion.

Pixel and display device including the same

A pixel of display device includes a light emitting element, a first transistor coupled between first power source and a second node and having a gate electrode connected to a first node N1, and the first transistor being configured to control a driving current supplied to the light emitting element in response to a voltage of the first node, a first capacitor including one electrode connected to the first node and another electrode connected to a third node, a second transistor coupled between the third node and a data line, a third transistor coupled between the first node and the second node, a fourth transistor coupled between the first node and an initialization power source, a fifth transistor coupled between a reference power source and the third node, and an eighth transistor coupled between a fourth node and an anode initialization power source.