A power reduced display includes a light source having an available space and configured to generate a backlight, a first display having multiple first pixels, wherein each first pixel is configured to selectively pass and block the backlight, a second display having multiple second pixels. The light source includes a first number of first packages each having a single light-emitting diode. The first number is a largest number of the first packages that fit in the available space of the light source. The first number of the first packages is configured to consume a first power to produce a particular luminance. A second number of second packages each having two light-emitting diodes alternatively fit in the available space and is configured to consume a second power to produce the particular luminance. The first number is greater than the second number. The first power is less than the second power.

Embodiments of the present application relate to the field of display driving technology, and disclose a method, an apparatus, an electronic device and a storage medium for processing pixel data. The method comprises: acquiring first image parameters of a first image unit and second image parameters of a second image unit, wherein the first image unit includes pixel data, of a first image, which is located on a first horizontal line, the second image unit includes pixel data, of a second image, which is located on the first horizontal line, and the second image is a previous frame of the first image; and updating the pixel data of the first image unit when the first image parameters do not match the second image parameters. The embodiments of the present application solve the problem of high driving power consumption in the process of outputting screens of the display panel in the prior art.

The present disclosure provides a driving circuit of a display panel and a display device. The driving circuit includes a gate-on-array (GOA) circuit transmitting a scan driving signal to the display panel through a corresponding gate signal line, and further includes a pull-down module and a control bus. The pull-down module is activated at a falling edge of a gate driving signal to accelerate a potential descent speed of the pull-down module, thereby increasing a charging time of a thin film transistor and realizing a narrow-frame display panel.

A pixel circuit and a display device including the same are disclosed. The pixel circuit includes a driving element including a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode to which a preset voltage is applied; a light emitting element including an anode electrode connected to a fourth node and a cathode electrode to which a low-potential power supply voltage is applied; a first switch element connected between the first node and the second node; a second switch element connected between the third node and the fourth node; a first capacitor connected to the first gate electrode of the driving element; and a second capacitor connected to the third node.

A scan driving circuit of a display device includes a first output terminal electrically connected to a first scan line, a second output terminal electrically connected to a second scan line, a first masking circuit electrically connecting the first output terminal and the second output terminal and outputting, as a first scan signal, a second scan signal to the first output terminal, a driving circuit outputting the second scan signal to the second output terminal in response to clock signals and a carry signal, and a second masking circuit masking the second scan signal to a predetermined level in response to the second masking signal, wherein the first masking circuit electrically disconnects the first output terminal from the second output terminal in response to a first masking signal.

Embodiments relate to a display device including two or more sections of pixels in a display area powered by supply voltages in power rails. The display device also includes two or more power detection circuits connected to two or more locations along the power rails to detect local voltages at the locations. Depending on an image being display during a frame, the two or more sections of pixels may cause changes in local voltages at the two or more locations. The detected local voltages are provided to two or more voltage regulators, and the two or more voltage regulators update supply voltages provided to the power rails to compensate for the changes in the local voltages.

An inverter circuit, a gate driver using the same, and a display device according to an embodiment are discussed. The inverter circuit can include a first transistor connected between a high potential voltage line and a first node; a second transistor having a gate connected to the first node and turned on according to a voltage of the first node to charge a second control node to a high potential voltage of the high potential voltage line; a third transistor having a gate connected to a first control node, a first electrode connected to the first node, and a second electrode connected to the second control node; and a fourth transistor having a gate connected to the first control node, a first electrode connected to the second control node, and a second electrode connected to a low potential voltage line.

Image data for a current image frame may be compensated for transient response variations due to variations in display panel temperatures at various positions of the display panel by performing pixel drive compensation. The pixel drive compensation may be performed based at least in part upon display panel temperatures at various portions of the display panel. In this way, drive compensation corresponding to various temperature variations in a display panel may be implemented.

Embodiments of the disclosed subject matter provide a device that includes an organic light emitting device (OLED), and a drive circuit to control the operation of the OLED, comprising a response time accelerator thin film transistor (TFT) configured to short or reverse bias the OLED for a predetermined period of time during a frame time. Other embodiments include an OLED having a plurality of sub-pixels, where one or more of sub-pixels configured to emit light of at least a first color comprises a first emissive area and a second emissive area that are independently controllable, where the first emissive area is larger than the second emissive area. The controller is configured to control the second emissive area to have (i) a higher brightness, and/or (ii) a higher current density than the first emissive area for a first sub-pixel luminance level that is less than a maximum luminance.

Systems, apparatuses, and methods for performing asynchronous memory clock changes on multiple displays are disclosed. From time to time, a memory clock frequency change is desired for a memory subsystem storing frame buffer(s) used to drive pixels to multiple displays. For example, when the real-time memory bandwidth demand differs from the memory bandwidth available with the existing memory clock frequency, a control unit tracks the vertical blanking interval (VBI) timing of a first display. Also, the control unit causes a second display to enter into panel self-refresh (PSR) mode. Once the PSR mode of the second display overlaps with a VBI of the first display, a memory clock frequency change, including memory training, is initiated. After the memory clock frequency change, the displays are driven by the frame buffer(s) in the memory subsystem at an updated frequency.