In one embodiment of the present invention a driver configures a graphics pipeline implemented in a cache tiling architecture to perform dynamically-defined multi-pass rendering sequences. In operation, based on sequence-specific configuration data, the driver determines an optimized tile size and, for each pixel in each pass, the set of pixels in each previous pass that influence the processing of the pixel. The driver then configures the graphics pipeline to perform per-tile rendering operations in a region that is translated by a pass-specific offset backwardvertically and/or horizontallyalong a tiled caching traversal line. Notably, the offset ensures that the required pixel data from previous passes is available. The driver further configures the graphics pipeline to store the rendered data in cache lines. Advantageously, the disclosed approach exploits the efficiencies inherent in cache tiling architecture while honoring highly configurable data dependencies between passes in multi-pass rendering sequences.

An apparatus to facilitate memory tiling is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads via access to the memory and tiling logic to apply a tiling pattern to memory addresses for data stored in the memory.

Conservative rasterization hardware comprises hardware logic arranged to perform an edge test calculation for each edge of a primitive and for two corners of each pixel in a microtile. The two corners that are used are selected based on the gradient of the edge and the edge test result for one corner is the inner coverage result and the edge test result for the other corner is the outer coverage result for the pixel. An overall outer coverage result for the pixel and the primitive is calculated by combining the outer coverage results for the pixel and each of the edges of the primitive in an AND gate. The overall inner coverage result for the pixel is calculated in a similar manner.

Conservative rasterization hardware comprises hardware logic arranged to perform an edge test calculation for each edge of a primitive and for two corners of each pixel in a microtile. The two corners that are used are selected based on the gradient of the edge and the edge test result for one corner is the inner coverage result and the edge test result for the other corner is the outer coverage result for the pixel. An overall outer coverage result for the pixel and the primitive is calculated by combining the outer coverage results for the pixel and each of the edges of the primitive in an AND gate. The overall inner coverage result for the pixel is calculated in a similar manner.

Certain aspects of the present disclosure provide techniques for scalably and efficiently converting linear image data into multi-dimensional image data for multimedia applications. In one example, a method for managing image data includes receiving a line of image data in a linear format via a system bus of width T, wherein the image data's native format is a tile format of H lines per tile; forming H subsets of image data from the line of image data in the linear format; writing the H subsets of image data to a memory comprising B.sub.N=H banks of B.sub.W=T/B.sub.N pixel width, wherein each subset of the H subsets is written to a different bank of the B.sub.N banks; and outputting the H subsets of image data in the tile format.

Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

An integrated circuit (IC) includes a video buffer memory and display driver circuitry. The video buffer memory includes a buffer memory map. The video buffer memory stores one or more raster lines of video data organized as tiled lines. Each of the tiled lines including two quartiles. The display driver circuitry is coupled to the video buffer memory. The display driver circuitry writes data associated with a portion of a first data line to a first one of the two quartiles of a first one of the tiled lines, and updates the buffer memory map. Further, the display driver determines a full display line being present within the video buffer memory based on the buffer memory map. The display driver further outputs the full display line to a display device.

Device localization (e.g., ultra-wideband device localization) may be used to provide coordinated outputs and/or receive coordinated inputs using multiple devices. Providing coordinated outputs may include providing partial outputs using multiple devices, modifying an output of a device based on its position and/or orientation relative to another device, and the like. In some cases, each device of a set of multiple devices may provide a partial output, which combines with partial outputs of the remaining devices to produce a coordinated output.

The present invention facilitates efficient and effective image processing. A network can comprise: a first system configured to perform a first portion of lighting calculations for an image and combing results of the first portion of lighting calculations for the image with results of a second portion of lighting calculations; and a second system configured to perform the second portion of lighting calculations and forward the results of the second portion of the lighting calculations to the first system. The first and second portion of lighting calculations can be associated with indirect lighting calculations and direct lighting calculations respectively. The first system can be a client in a local location and the second system can be a server in a remote location (e.g., a cloud computing environment). The first system and second system can be in a cloud and a video is transmitted to a local system.

The present disclosure relates to a video wall. The video wall according to an embodiment of the present disclosure comprises: a plurality of displays; an image divider configured to divide an input image into a plurality of images; and at least one controller, wherein in response to a video being repeatedly played back, the at least one controller is configured to calculate an accumulated luminance value for each block on the plurality of displays during a first period when the video is repeatedly played back and calculate a luminance compensation value for each block based on the calculated accumulated luminance, and the plurality of displays display the video based on the luminance compensation value during a second period following the first period. Accordingly, an afterimage occurring due to the repeatedly played video may be reduced.