Disclosed are an image data reading method and apparatus, an electronic device, and a readable storage medium, relating to the technical field of LED image display. The image data reading method includes: storing image data in each row of image blocks into a number of v storage blocks, where each of the v storage blocks stores a number of h rows, each row of data including image data stored at a same position of each group in a same row of every image block; and sequentially outputting from each of the v storage blocks by: sequentially reading each row of the image data in a vertical order, and simultaneously outputting the image data stored at the same position.

A pixel circuit includes a capacitor, a light emitting control transistors, a driving transistor, and multiple light emitting transistors. The light emitting control transistor includes a gate electrode coupled to a light emitting control signal, a source electrode coupled to a supply voltage, and a drain electrode. The driving transistor includes a gate electrode coupled to the capacitor, a source electrode coupled to the drain electrode of the light emitting control transistor, and a drain electrode. Each light emitting transistor includes a gate electrode coupled to a respective light emitting signal, a source electrode coupled to the drain electrode of the driving transistor, and a drain electrode coupled to a respective light emitting element. Each light emitting signal turns on the respective light emitting transistor during a respective light emitting period within a frame period to cause the respective light emitting element to emit a light. The light emitting control signal turns on the light emitting control transistor during each light emitting period within the frame period.

If the picture complexity is low then the number of pixels in a frame may be reduced. For example, pixel-to-pixel variation in terms of RGB color values can be used to determine the complexity of the frame. Frames can be characterized, in one embodiment, as non-complex frames with less pixel variation and complex frames with very high pixel variation. The high PPI may be used only for complex frames while non-complex frames can use low PPI. This method reduces memory fetching and pixel processing within the display engine and thereby saves power.

Apparatus for data communications includes a host interface, which is configured to be connected to a bus of a host computer having a processor and a memory. Processing circuitry, which is coupled to the host interface, is configured to receive video data with respect to a sequence of pixels, the video data including data words of more than eight bits per pixel for at least one pixel component of the pixels, and to write the video data, via the host interface, to at least one buffer in the memory while justifying the video data in the memory so that the successive pixels in the sequence are byte-aligned in the at least one buffer.

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.

Certain aspects of the present disclosure provide techniques for scalably and efficiently converting linear image data into multi-dimensional image data for multimedia applications. In one example, a method for managing image data includes receiving a line of image data in a linear format via a system bus of width T, wherein the image data's native format is a tile format of H lines per tile; forming H subsets of image data from the line of image data in the linear format; writing the H subsets of image data to a memory comprising B.sub.N=H banks of B.sub.W=T/B.sub.N pixel width, wherein each subset of the H subsets is written to a different bank of the B.sub.N banks; and outputting the H subsets of image data in the tile format.

A pixel circuit includes a capacitor, a light emitting control transistor, a driving transistor, and multiple light emitting transistors. The light emitting control transistor includes a gate electrode coupled to a light emitting control signal, a source electrode coupled to a supply voltage, and a drain electrode. The driving transistor includes a gate electrode coupled to the capacitor, a source electrode coupled to the drain electrode of the light emitting control transistor, and a drain electrode. Each light emitting transistor includes a gate electrode coupled to a respective light emitting signal, a source electrode coupled to the drain electrode of the driving transistor, and a drain electrode coupled to a respective light emitting element. Each light emitting signal turns on the respective light emitting transistor during a respective light emitting period within a frame period to cause the respective light emitting element to emit a light. The light emitting control signal turns on the light emitting control transistor during each light emitting period within the frame period.

Aspects of the disclosure provide a method for merging compressed access units according to compression rates and/or positions of the respective compressed access units. The method can include receiving a sequence of compressed access units corresponding to a sequence of raw access units partitioned from an image or a video frame and corresponding to a sequence of memory spaces in a frame buffer, determining a merged access unit including at least two consecutive compressed access units based on compression rates and/or positions of the sequence of compressed access units. The merged access unit is to be stored in the frame buffer with a reduced gap between the at least two consecutive compressed access units compared with storing the at least two consecutive compressed access units in corresponding memory spaces in the sequence of memory spaces.

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.

There is provided a method of a graphics processing system, the method including receiving dependency information for a set of interdependent images indicating a dependency across one or more compute shader and graphics workloads, and interleaving processing of the compute shader and graphics workloads for the set of interdependent images in accordance with the dependency information without recompiling a compute shader generating the one or more compute shader workloads.