Please replace the originally filed abstract with the abstract provided below: A method for operating a display comprising providing a first feed of a first sequence of image data and providing a second feed of a second sequence of image data, the second feed comprising a second sequence of image data and a second complementary sequence of image data. The display is operated at a high display frame rate (HDFR) comprising HDFR image slots/slices during a standard frame rate (SFR) time interval. The method includes displaying the first feed and the second feed in a time-sliced multiplexed manner in the HDFR image slots of each SFR time interval. The first feed and the second feed comprise gray images obtained from the combination of image data presented at equal luminance and being evenly distributed within the HDFR image slots so the luminance changes of the display occur at frequencies greater than or equal to twice the SFR.

There is provided a method of a graphics processing system, the method including receiving dependency information for a set of interdependent images indicating a dependency across one or more compute shader and graphics workloads, and interleaving processing of the compute shader and graphics workloads for the set of interdependent images in accordance with the dependency information without recompiling a compute shader generating the one or more compute shader workloads.

System address reconstruction logic in accordance with one embodiment of the present description, reconstructs a system address from a channel address translated from the system address. The system address reconstruction logic includes logic configured to reconstruct one or more systems address fields as a function of the channel address, the number of memory controller target ways of the memory being equal to three, the number of bits of the granularity of interleaving of data among the memory controller target ways, the number of channels per memory controller target way, and the number of bits of the granularity of interleaving of data among the channels of a memory controller target way. Other aspects are described herein.

A controller includes a frame memory configured to store an image frame, a frame memory controller coupled to the frame memory and configured to obtain image data from the image frame. The image data is associated with a color component of the image frame. The controller also includes a dither noise mask generator configured to provide dither noise masks according to dither noise levels for the image data, and a bit plane generator coupled to the frame memory controller and the dither noise mask generator and configured to generate bit planes based on the dither noise masks for the image data.

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.

If the picture complexity is low then the number of pixels in a frame may be reduced. For example, pixel-to-pixel variation in terms of RGB color values can be used to determine the complexity of the frame. Frames can be characterized, in one embodiment, as non-complex frames with less pixel variation and complex frames with very high pixel variation. The high PPI may be used only for complex frames while non-complex frames can use low PPI. This method reduces memory fetching and pixel processing within the display engine and thereby saves power.

An apparatus includes a graphics pipeline and a pixel data reordering module. The graphics pipeline is configured to generate a plurality pieces of pixel data of a frame. The plurality pieces of pixel data of the frame are associated with a first order in which the plurality pieces of pixel data of the frame are to be provided to a display panel having an array of pixels. Each piece of pixel data of the frame corresponds to one pixel of the array of pixels. The array of pixels are divided into a plurality of groups of pixels. The pixel data reordering module is configured to cause the plurality pieces of pixel data of the frame to be obtained by the display panel in a second order. The second order is determined based on at least a manner in which the array of pixels are divided into the groups of pixels.

An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated memories that use separate power domains. Data of a given type is stored in an interleaved manner among the multiple memories. When control circuitry detects an idle state, commands are sent to the multiple memories specifying storing data of the given type in a contiguous manner in the memories connected to multiple functional blocks. Subsequently, the control circuitry transitions all but one of the memories to the sleep state. The memories rotate amongst themselves with a single memory being in the active state and servicing requests based on which data of the given type is targeted by the requests.

An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated functional blocks that use separate power domains. Data of a given type is stored in an interleaved manner among the multiple functional blocks. When control circuitry detects a low-performance mode, commands are sent to the multiple functional blocks specifying storing data of the given type in a contiguous manner in one or more of the caches of the multiple functional blocks and the memories connected to the multiple functional blocks. Following, the control circuitry transitions the memories to a sleep state and transitions all but one of the functional blocks to the sleep state. The functional blocks rotate amongst themselves with a single functional block being in the active state and servicing requests based on which data of the given type is targeted by the requests.

An electronic paper display apparatus including an electronic paper display panel to display an image page, a display driver coupled to the electronic paper display panel, and a data processor coupled to the display driver. The display driver drives the electronic paper display panel to display a plurality of image frames according to image data, so as to display the image page. The data processor converts a first look-up table into a second look-up table and merges a current frame and a previous frame into a combined frame. The data processor generates the image data according to the combined frame and the second look-up table and outputs the image data. The image frames include the current frame and the previous frame. A driving method of the electronic paper display apparatus is also provided.