Systems, apparatuses, and methods for implementing a timestamp based display update mechanism. A display control unit includes a timestamp queue for storing timestamps, wherein each timestamp indicates when a corresponding frame configuration set should be fetched from memory. At pre-defined intervals, the display control unit may compare the timestamp of the topmost entry of the timestamp queue to a global timer value. If the timestamp is earlier than the global timer value, the display control unit may pop the timestamp entry and fetch the frame next configuration set from memory. The display control unit may then apply the updates of the frame configuration set to its pixel processing elements. After applying the updates, the display control unit may fetch and process the source pixel data and then drive the pixels of the next frame to the display.

A system includes a display subsystem. The display subsystem includes a shared buffer having allocated portions, each allocated to one of a plurality of display threads, each display thread associated with a display peripheral. The display subsystem also includes a direct memory access (DMA) engine configured to receive a request from a main processor to deallocate an amount of space from a first allocated portion associated with a first display thread. In response to receiving the request, the DMA engine deallocates the amount of space from the first allocated portion and shifts the allocated portions of at least some of other display threads to maintain contiguity of the allocated portions and concatenate free space at an end of the shared buffer.

A video processing system includes a storage device, a receiving circuit, an audio/video demultiplexing circuit, a video decoder, and a display engine. The storage device includes a data buffer, a bitstream buffer, and a display buffer. An output of the receiving circuit is written into the data buffer. An input of the audio/video demultiplexing circuit is read from the data buffer, and an output of the audio/video demultiplexing circuit is written into the bitstream buffer. An input of the video decoder is read from the bitstream buffer, and an output of the video decoder is written into the display buffer. An input of the display engine is read from the display buffer. Each of the data buffer, the bitstream buffer, and the display buffer is a ring buffer.

An electronic device may include a display panel and an image data source designed to determine a differing region in the image frame by comparing source image data and image data corresponding with a previous image frame. The electronic device may also include a display pipeline between the image data source and the display panel. The display pipeline may include image processing circuitry to convert image data from a source space to a display space and image processing circuitry to spatially process the image data. The display pipeline may determine a crop region by converting the differing region to the display space and determine a partial frame region, based on the image data to be spatially processed, by the image processing circuitry. The display pipeline may also determine and retrieve a fetch region smaller than the image frame by converting the partial frame region to the source space.

A display device that is driven with low power and a method for operating the display device are provided. The display device includes a host; a controller to which a first signal is supplied from the host; and a display panel to which a second signal is supplied from the controller. When the first signal includes image data, the first signal includes a command indicating the presence of the image data. When the controller detects the command, the controller supplies the image data as the second signal. When the controller does not detect the command, the controller stops supplying the second signal. After the controller stops supplying the second signal for a predetermined time, the controller resumes supplying the second signal regardless of whether or not the first signal includes the command.

A display method and a terminal device are provided, so as to resolve a prior-art problem that CPU power consumption of the terminal device is relatively high because a display system of the terminal device processes three procedures in parallel in a Vsync period. The method is: determining, by the display system of the terminal device, a start moment of a first procedure in an (M+1).sup.th Vsync period according to first processing duration of the first procedure in an M.sup.th Vsync period, so that the display system starts to execute a device display procedure before starting to execute the first procedure, the display system delays executing the first procedure in the (M+1).sup.th Vsync period, so that a time required for processing three procedures in parallel in the (M+1).sup.th Vsync period by the display system is reduced, and CPU power consumption of the terminal device is reduced.

Disclosed herein are techniques to provide both asynchronous frame updates and panel self-refresh in a single implementation. A platform can be arranged to provide frame updates asynchronously with the refresh rate of a connected panel while the connected panel can be arranged to self-refresh where no new updates are provided.

A system includes a display subsystem. The display subsystem includes a shared buffer having allocated portions, each allocated to one of a plurality of display threads, each display thread associated with a display peripheral. The display subsystem also includes a direct memory access (DMA) engine configured to receive a request from a main processor to deallocate an amount of space from a first allocated portion associated with a first display thread. In response to receiving the request, the DMA engine deallocates the amount of space from the first allocated portion and shifts the allocated portions of at least some of other display threads to maintain contiguity of the allocated portions and concatenate free space at an end of the shared buffer.

The present invention provides a persistence of vision (POV) display device using a light emitting element, the display device comprising: a fixed module including a motor; a rotating module located on the fixed module and rotated by the motor; at least one panel coupled to the rotating module; a plurality of light sources arranged on the panel and having a plurality of pixels; a light source module including a light emitting element array in which the plurality of light sources are arranged in a longitudinal direction; memory that stores video data received from an external source device; and a controller that controls the order of input of the video data and the order of output of the video data.

The present teaching relates to method, system, medium, and implementations for LED display. A first signal is received that signals a timing for a next data transfer. In response to the first signal, a bit-based image block stored in a memory is transferred, via a bus connected thereto, to one of a pair of alternate buffers pointed to by a write buffer pointer, which is subsequently toggled to point to another of the pair of alternate buffers. A second signal is received that signals a timing for refreshing the LED display. In response to the second signal, the bit-based image block is retrieved from the one of the pair of alternate buffers pointed to by a read buffer pointer, which is then toggled to point to the other of the pair of alternate buffers. The lights of the LED display are then refreshed in accordance with control signals generated based on the bit-based image block.