A display device which can display a clear image and can display an image with low power consumption is provided. The display device includes an arithmetic circuit having a function of generating first to third display data, a first display portion, and a second display portion. The arithmetic circuit has a function of detecting a color region and a gray-scale region of the generated first display data and generating the second display data corresponding to an image to be displayed on the first display portion and the third display data corresponding to an image to be displayed on the second display portion, on the basis of the detection results.

Systems and method for synchronizing access to buffered data are disclosed. In such a method, video data is buffered in a frame buffer memory by a producer device. A write level indicator is provided to a synchronizer by the producer device. A read level indicator is provided to the synchronizer by a consumer device. The synchronizer compares the write level indicator with the read level indicator to determine a difference. The consumer device is informed by the synchronizer when the difference meets a sub-frame threshold. The consumer device reads the buffered data from the frame buffer memory on a sub-frame-by-sub-frame basis responsive to the informing.

An information processing device includes: a timing controller; a system device; and a display panel. The system device operates in accordance with at least a first operating system (OS) and a second OS, and outputs first original image data from the first OS and second original image data from the second OS to the timing controller. The display panel includes a plurality of pixels arranged in a predetermined display area. The timing controller includes: a memory; a writing unit; and a reading unit. The memory has a storage area associated with the display area. The writing unit stores the first original image data in a first individual storage area assigned to the first OS in the storage area, and stores the second original image data in a second individual storage area assigned to the second OS in the storage area. The reading unit reads image data stored in the storage area, frame by frame, and outputs the image data to the display panel.

In one embodiment, an apparatus having an integrated circuit made of substrate, at least three light emitters arranged on the substrate, and driver circuitry located on the integrated circuit, the driver circuitry to drive an ultra low persistence display to remove ghosting and nausea.

A display device includes a display panel, a frame memory, a display control circuit that performs a predetermined process on a first video signal using the frame memory and outputs an obtained second video signal, and a panel drive circuit that drives the display panel based on the second video signal. The display control circuit checks whether the frame memory is normal or abnormal, by storing partial video data included in the first video signal, writing to the frame memory, video data obtained by replacing the partial video data with first test data, and comparing with the first test data, second test data included in the video data read from the frame memory.

Systems, apparatuses, and methods for aggregating memory requests with opportunism in a display pipeline. Memory requests are aggregated for each requestor of a plurality of requestors in the display pipeline. When the number of memory requests for a given requestor reaches a corresponding threshold, memory requests may be issued for the given requestor. In response to determining the given requestor has reached its threshold, other requestors may issue memory requests even if they have not yet aggregated enough memory requests to reach their corresponding thresholds.

In one embodiment, an apparatus having an integrated circuit made of substrate, at least three light emitters arranged on the substrate, and driver circuitry located on the integrated circuit, the driver circuitry to drive an ultra low persistence display to remove ghosting and nausea.

This application provides an electronic device, to reduce a probability that a screen stalling phenomenon. A timing control unit sends one first pulse of a tearing effect signal every a first preset time T1. The timing control unit sends S second pulses of the tearing effect signal when a transceiver unit does not receive an N.sup.th frame of display data within a preset time. The processing unit receives the N.sup.th frame of display data in the (N+1).sup.th frame, and controls, based on the N.sup.th frame of display data, the display to display an N.sup.th frame of image.

HDMI transmission of uncompressed image data, on which dynamic range processing is performed, is performed from an HDMI source device and a display in appropriate luminance is performed in an HDMI sink device. When HDMI input switching is performed, a television receiver 13 transmits transmission request information to an HDMI source device in a destination of the input switching and acquires dynamic range conversion definition information of uncompressed image data at intended timing. Also, when it is possible to acquire the dynamic range conversion definition information of the uncompressed image data, the television receiver 13 minimizes transmission of the dynamic range conversion definition information from a BD recorder 11 by sending reception recognition information back.

A novel bit storage circuit includes a first voltage supply line, a second voltage supply line, a bit line, a latch, a first switching transistor, and a blocking transistor. The latch includes an input and an output. The first switching transistor includes a first terminal, a second terminal, and a control terminal. The first switching transistor is operative to provide a conductive path and a non-conductive path between the bit line and the input of the latch responsive to a first control signal being asserted on the control terminal of the first switching transistor. The blocking transistor includes a control terminal and is operative to selectively provide a conductive path and a non-conductive path between the input of the latch and the second voltage supply line responsive to a second control signal. The blocking transistor facilitates the use of a single bit line.