The embodiment of the disclosure discloses a method for processing data, a device for processing data, a system for processing data, a system controller and a mudure controller. The method includes: receiving input image data; storing the image data into a memory; reading target image data from the memory according to loaded area information of at least one output portal, wherein the output portal is electrically connected with a display screen, and the loaded area information of the output portal characterizes a target display area of the display screen; compressing the target image data to reduce the data volume of the target image data to meet a output bandwidth of the output portal to obtain compressed image data characterized by a plurality of image data packets; and outputting the compressed image data through the output portal.

The present disclosure relates to the field of display technology, and provides a display panel and a driving method thereof, a compensation data compression method and a compensation data decompression method. The display panel includes a data compression unit and a data decompression unit. The data compression unit is used to acquire a plurality of first compensation data and a common parameter, and compress each of the first compensation data into second compensation data according to a preset compression rule based on the first compensation data and the common parameter. The data decompression unit is used to acquire a plurality of second compensation data and the common parameter, and decompress each of the second compensation data into the first compensation data according to a preset decompression rule based on the second compensation data and the common parameter.

A low power architecture for mobile displays includes a display, a low voltage integrated circuit configured to: receive a high speed input signal; process the input signal; and output uncompressed pixel data based on the processed input signal; and a high voltage integrated circuit configured to drive pixels in the display based on the uncompressed pixel data; wherein the low voltage integrated circuit is configured to provides the uncompressed pixel data to the high voltage integrated circuit via a timing-to-driver (T2D) interface.

Aspects of the disclosure provide a method for merging compressed access units according to compression rates and/or positions of the respective compressed access units. The method can include receiving a sequence of compressed access units corresponding to a sequence of raw access units partitioned from an image or a video frame and corresponding to a sequence of memory spaces in a frame buffer, determining a merged access unit including at least two consecutive compressed access units based on compression rates and/or positions of the sequence of compressed access units. The merged access unit is to be stored in the frame buffer with a reduced gap between the at least two consecutive compressed access units compared with storing the at least two consecutive compressed access units in corresponding memory spaces in the sequence of memory spaces.

HDMI transmission of uncompressed image data, on which dynamic range processing is performed, is performed from an HDMI source device and a display in appropriate luminance is performed in an HDMI sink device. When HDMI input switching is performed, a television receiver 13 transmits transmission request information to an HDMI source device in a destination of the input switching and acquires dynamic range conversion definition information of uncompressed image data at intended timing. Also, when it is possible to acquire the dynamic range conversion definition information of the uncompressed image data, the television receiver 13 minimizes transmission of the dynamic range conversion definition information from a BD recorder 11 by sending reception recognition information back.

A pixel circuit, a display panel, a display device and a driving method thereof are provided. The display panel includes a silicon substrate and a plurality of display units and a plurality of storage units fabricated on the silicon substrate. The plurality of storage units correspond to the plurality of display units one to one, and the plurality of storage units are respectively configured to receive and store display data of the plurality of display units corresponding to the plurality of storage units.

A display controller includes a variable refresh rate circuit. The variable refresh rate circuit is configured to receive a first video frame, and provide a first dithered segment of the first video frame comprising instructions to display the first dithered segment during reception of a second video frame. The variable refresh rate circuit is also configured to, responsive to reception of the second video frame and completion of display of the first dithered segment, provide a second dithered segment of the second video frame comprising instructions to display the second dithered segment.

The disclosure provides an image data transmission device including: receiving sub-circuit, writing control component, and reading control component. The disclosure further provides an image data transmission method, including: in response to the receiving sub-circuit being in locked state, receiving, by receiving sub-circuit, image data sent by a mainboard, and writing, according to a first frame synchronous signal, the image data received from the mainboard in each clock cycle of the first frame synchronous signal into a frame of a memory, reading, according to a second frame synchronous signal, a frame from the memory in each clock cycle of the second frame synchronous signal; sending each frame read from the memory to a display component; and in response to the receiving sub-circuit being in unlocked state, stopping writing the image data into the memory. The disclosure further provides an electronic apparatus, a computer-readable medium and a display system.

A display controller comprises an input stage 20 operable to read at least one input surface, a composition stage 28 operable to compose plural input surfaces to generate a composited output surface, an output stage 30 operable to provide the composited output surface to a display for display, a scaling engine 31 operable to scale a composited output surface generated by the composition stage 28, and a write-out stage 32 operable to write a composited and/or scaled output surface to external memory.

Disclosed are a memory device and a read/write method of the memory device and, more particularly, a memory device and a read/write method of the memory device capable of reducing power consumption of a display device by reducing a storage operation and an output operation of the memory device for a plurality of pieces of pixel data.