A hybrid memory includes a plurality of tiles including a plurality of rows including a first row having a first type of memory cells and a second row having a second type of memory cells; a pair of bitline select signals including a bitline select signal and a bitline select bar signal that is an inverse of the bitline select signal; a wordline driver that is configured to receive an input data; a sense amplifier that is configured to output an output data; a write bitline coupled to the first row and the second row; a read bitline coupled to the first row and the second row; a wordline coupled to each of the plurality of rows; and a bitline that is coupled to the write bitline and the read bitline based on set values of the pair of bitline select signals.

A display device includes a memory, a timing controller including a scaler, and a processor, wherein the processor is configured to generate, via the scaler, a first sync signal based on an input timing of at least one piece of background image data, generate, via the scaler, a second sync signal based on an input timing of at least one piece of region of interest (ROI) image data, transmit, to the scaler, the at least one piece of background image data output from the memory during a first period according to the first sync signal, and transmit, to the scaler, the at least one piece of ROI image data output from the memory during a second period according to the second sync signal.

In one embodiment, an apparatus having an integrated circuit made of substrate, at least three light emitters arranged on the substrate, and driver circuitry located on the integrated circuit, the driver circuitry to drive an ultra low persistence display to remove ghosting and nausea.

A hybrid memory includes a plurality of tiles including a plurality of rows including a first row having a first type of memory cells and a second row having a second type of memory cells; a pair of bitline select signals including a bitline select signal and a bitline select bar signal that is an inverse of the bitline select signal; a wordline driver that is configured to receive an input data; a sense amplifier that is configured to output an output data; a write bitline coupled to the first row and the second row; a read bitline coupled to the first row and the second row; a wordline coupled to each of the plurality of rows; and a bitline that is coupled to the write bitline and the read bitline based on set values of the pair of bitline select signals.

The display controller (1) includes: a DRAM (31); a SRAM (32) which consumes electric power less than the DRAM (31); an update judging section (61); a secondary compression section (70); and a decompression section (40). In a case where the update judging section (61) has judged that image data is not updated, (i) the secondary compression section (70) compresses image data and then stores compressed image data in the SRAM (32), (ii) the DRAM (31) stops a memory retaining operation, and (iii) the decompression section (40) decompresses the compressed image data and then supplies decompressed data to an LCD (3).

In general, techniques are described for performing multi-layer image fetching using a single hardware image fetcher pipeline of a display processor. A device comprising a layer buffer, and a display processor may be configured to perform the techniques. The layer buffer may be configured to store two or more independent layers. The display processor may include a single hardware image fetcher pipeline. The single hardware image fetcher pipeline may be configured to concurrently retrieve, from the layer buffer, two or more independent layers, concurrently process the two or more independent layers, and concurrently output, by two or more outputs of the single hardware image fetcher pipeline, the two or more processed independent layers for composition to form one of the frames to be displayed by one or more display units.

A display recording information and generation method thereof are disclosed. The display recording information is used to record the corresponding relationship between the display information received by a driving IC of a display and pixels of the display. The display recording information is formed by one byte (8 bits). Its first bit through six bit record a counting result that a number counter or a column counter performs a six-bit counting on a number of pixels or a number of columns of pixels starting from 0; its seventh bit uses 0 or 1 to record that the counting result belongs to the number of pixels or a number of columns of pixels; its eighth bit uses 1 to record that a most significant bit of the display information including red, green, or blue is 1, otherwise uses 0 to record.

Aspects of the disclosure provide a method and device for storing an input image into a memory. The disclosure describes allocating one or more frame buffers in the memory. The disclosure further describes dividing the input image into access units corresponding to subsets of the input image and allocating a main portion and a secondary portion in the frame buffer for each of the access units, wherein at least one of the secondary portions is not sequentially located after its respective main portion within the frame buffer. The disclosure also describes compressing the access units into compressed access units and storing each of the compressed access units into its respective main portion, and if a size of the compressed access unit exceeds a size of the main portion, then storing a remainder of the compressed access unit into its respective secondary portion.

Aspects of the disclosure provide a method for merging compressed access units according to compression rates and/or positions of the respective compressed access units. The method can include receiving a sequence of compressed access units corresponding to a sequence of raw access units partitioned from an image or a video frame and corresponding to a sequence of memory spaces in a frame buffer, determining a merged access unit including at least two consecutive compressed access units based on compression rates and/or positions of the sequence of compressed access units. The merged access unit is to be stored in the frame buffer with a reduced gap between the at least two consecutive compressed access units compared with storing the at least two consecutive compressed access units in corresponding memory spaces in the sequence of memory spaces.

According to an example aspect of the present invention, there is provided an apparatus comprising a first processing core configured to generate first control signals and to control a display by providing the first control signals to the display via a first display interface, a second processing core configured to generate second control signals and to control the display by providing the second control signals to the display via a second display interface, and the first processing core being further configured to cause the second processing core to enter and leave a hibernation state based at least partly on a determination, by the first processing core, concerning an instruction from outside the apparatus.