A method, at a host device (10), of managing memory (28) of a display control device (16), the memory (28) being used for storing display data sent from the host device (10) to the display control device (16) for display. The method involves maintaining a map (18) at the host device (10) corresponding to the memory (28) at the display control device, the map (18) indicating locations corresponding to addresses of the memory (28) at which data is stored or not. The map (18) is used to determine a size of a portion of the display data, and a location on the map (18) where the portion of display data would fit into the memory. An address in the memory (28) corresponding to the determined location on the map (18), together with the portion of display data, is then sent to the display control device (16), and the location on the map (18) corresponding to the address in the memory (28) is updated to indicate that the address has data stored in it. The data may be compressed using compression parameters, which can be selected so that the compressed portion of display data will fit into a free space in the memory (28) of the display control device (16).

An apparatus and a method for video frame rotation are provided. The apparatus includes a synchronous dynamic random access memory (SDRAM) and a video rotation circuit. The video rotation circuit is coupled to the SDRAM. The video rotation circuit sequentially writes a plurality of pixels of a video frame into the SDRAM in a row-by-row scanning manner. The video rotation circuit divides a plurality of columns of the video frame into a plurality of column sets, so as to divide each of the rows of the video frame into a plurality of sub-rows. The video rotation circuit performs an internal column-set scanning for each of the column sets in a column-set-by-column-set manner, so as to discretely read the sub-rows from the SDRAM.

A data processing method and device for a Light emitting diode (LED) Television (TV), and an LED TV are disclosed, the data processing device includes: a signal processing chip configured to perform mode conversion on a received TV signal so as to obtain a first video signal of a preset mode; and a video processing chip connected to the signal processing chip and configured to perform clock synchronization processing on the first video signal so as to obtain a second video signal and output the second video signal to an LED display. The problem in the prior art that an LED TV can only display a TV signal of a single mode is solved, thereby achieving the effect that the LED TV can display videos of various modes and various formats.

A stereo viewpoint graphics processing subsystem and a method of sharing geometry data between stereo images in screen-space processing. One embodiment of the stereo viewpoint graphics processing subsystem configured to render a scene includes: (1) stereo frame buffers configured to contain respective pixel-wise rendered scene data for stereo images, and (2) a sharing decision circuit operable to determine when to share geometric data between the stereo frame buffers for carrying out screen-space effect processes to render the scene in the stereo images.

A color display that can deactivate colors based on one or more criteria is disclosed. Reducing the number of color channels used to display an image may help conserve power, which may help extend the operating life of a battery-operated device. The display includes a backplane that is segmented by color to enable the deactivation. The segmentation may also reduce electrical loading on the electrical lines used to address the pixels in the backplane.

To prevent tearing in a case where image data is compressed to be written into a frame memory, the present invention includes (i) a compression section (33) for compressing image data for a single frame, the image data being transferred from a host processor (2), and writing the image data into a frame memory (31), (ii) an expansion section for reading image data, expanding the image data, and transferring the image data to an LCD (4), and (iii) a delay control section (32) for, until an inhibit time period Ts passes after the start of reading image data for a first frame, inhibiting the start of writing image data.

A display recording information and generation method thereof are disclosed. The display recording information is used to record the corresponding relationship between the display information received by a driving IC of a display and pixels of the display. The display recording information is formed by one byte (8 bits). Its first bit through six bit record a counting result that a number counter or a column counter performs a six-bit counting on a number of pixels or a number of columns of pixels starting from 0; its seventh bit uses 0 or 1 to record that the counting result belongs to the number of pixels or a number of columns of pixels; its eighth bit uses 1 to record that a most significant bit of the display information including red, green, or blue is 1, otherwise uses 0 to record.

HDMI transmission of uncompressed image data, on which dynamic range processing is performed, is performed from an HDMI source device and a display in appropriate luminance is performed in an HDMI sink device.

When HDMI input switching is performed, a television receiver 13 transmits transmission request information to an HDMI source device in a destination of the input switching and acquires dynamic range conversion definition information of uncompressed image data at intended timing. Also, when it is possible to acquire the dynamic range conversion definition information of the uncompressed image data, the television receiver 13 minimizes transmission of the dynamic range conversion definition information from a BD recorder 11 by sending reception recognition information back.

A novel bit storage circuit includes a first voltage supply line, a second voltage supply line, a bit line, a latch, a first switching transistor, and a blocking transistor. The latch includes an input and an output. The first switching transistor includes a first terminal, a second terminal, and a control terminal. The first switching transistor is operative to provide a conductive path and a non-conductive path between the bit line and the input of the latch responsive to a first control signal being asserted on the control terminal of the first switching transistor. The blocking transistor includes a control terminal and is operative to selectively provide a conductive path and a non-conductive path between the input of the latch and the second voltage supply line responsive to a second control signal. The blocking transistor facilitates the use of a single bit line.

A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.