The card reader includes a peak detector that detects a peak point of a reproduced signal according to a threshold. The peak detector applies, to a first peak value to be determined, a second peak value immediately before the first peak value, a third peak value, which is the second preceding peak value with respect to the first peak value, and a next peak value. When a difference between a first intermediate value, which is a value between the third peak value and the second peak value, and a second intermediate value, which is a value between the second peak value and the first peak value, is greater than or equal to a first difference value, the peak detector ignores a first threshold, and decides the first peak value after confirming that a digital value corresponding to the next peak value has exceeded a second threshold.

A peak detecting unit includes: a judging section, judging whether a current digital value produced by an AD converter has changed from a prior digital value; a holding section, being capable of holding the digital value output from the AD converter as an extreme value and its position information; and an updating section which, when the current digital value has changed from the prior digital value, updating the extreme value and its position information held in the holding section with the current digital value as a current extreme value and its position information, or when the current digital value matches the prior digital value, acquiring the intermediate position between the position of the current digital value and the position of the prior digital value as a current extreme value position, holding the matching digital value as a current extreme value, and updating the position information with the intermediate position information.

A method of reading servo wedge data from a rotating constant-density magnetic storage medium having a plurality of tracks, where each track is written at a track pattern frequency, the respective track pattern frequencies varying from a lowest frequency at an innermost one of the tracks to a highest frequency at an outermost one of the tracks, includes, for each respective track, determining, based on the pattern frequency of the respective track, a desired sampling position, sampling actual samples of servo wedge data based on a sampling clock used for all tracks, having a sampling frequency at least equal to the track pattern frequency of the outermost track, determining a phase relationship of the desired sampling position to the sampling clock, and, depending on the phase relationship between the sampling position and the sampling clock, interpolating a sample, or omitting interpolation of a sample and squelching the interpolation clock.

A method of reading servo wedge data from a rotating constant-density magnetic storage medium having a plurality of tracks, where each track is written at a track pattern frequency, the respective track pattern frequencies varying from a lowest frequency at an innermost one of the tracks to a highest frequency at an outermost one of the tracks, includes, for each respective track, determining, based on the pattern frequency of the respective track, a desired sampling position, sampling actual samples of servo wedge data based on a sampling clock used for all tracks, having a sampling frequency at least equal to the track pattern frequency of the outermost track, determining a phase relationship of the desired sampling position to the sampling clock, and, depending on the phase relationship between the sampling position and the sampling clock, interpolating a sample, or omitting interpolation of a sample and squelching the interpolation clock.

Disclosed are systems, methods, and devices for increasing the storage areal density of a storage device. In one embodiment, a method is disclosed comprising receiving host data, the host data including first data and extra bit data; generating run-length limited (RLL) data by encoding the first data with an RLL encoder; generating a symbol corresponding to at least one bit of the extra bit data; and generating superpositioned data by inserting the symbol within a contiguous section of repeating bits in the RLL-encoded first data.

Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase interpolator. The controller is configured to provide a digital timing code to the phase interpolator, and the phase interpolator is configured to apply a correction to the received digital timing code based, at least in part, on phase interpolator error correction data from a data structure containing phase interpolator error correction data.

In one embodiment, a method includes writing data to a storage medium, via a write channel, by applying a partial reverse concatenated modulation code to the data prior to storing encoded data to the storage medium. The applying the partial reverse concatenated modulation code to the data includes application of a C2 encoding scheme to the data to produce C2-encoded data prior to application of one or more modulation encoding schemes to the C2-encoded data to produce modulated data, followed by application of a C1 encoding scheme to the modulated data subsequent to the application of the one or more modulation encoding schemes to produce the encoded data.

Disclosed are systems, methods, and devices for increasing the storage areal density of a storage device. In one embodiment, a method is disclosed comprising receiving host data, the host data including first data and extra bit data; generating run-length limited (RLL) data by encoding the first data with an RLL encoder; generating a symbol corresponding to at least one bit of the extra bit data; and generating superpositioned data by inserting the symbol within a contiguous section of repeating bits in the RLL-encoded first data.

Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase interpolator. The controller is configured to provide a digital timing code to the phase interpolator, and the phase interpolator is configured to apply a correction to the received digital timing code based, at least in part, on phase interpolator error correction data from a data structure containing phase interpolator error correction data.

An apparatus according to one embodiment includes a hardware based controller that is configured to perform operations. The operations include performing anti-aliasing filtering on each of a plurality of signals, each signal having a frequency that is a different fraction of a frequency of a data read clock. An amplitude is measured of each of the signals after the anti-aliasing filtering. Moreover, the operations include determining whether the measured amplitudes of the signals are within a predefined range. Anti-aliasing settings used during the anti-aliasing filtering are stored in response to a determination that the amplitudes of the signals are within the predefined range. The anti-aliasing settings are changed in response to a determination that the amplitudes of the signals are outside the predefined range.