A magnetic recording array includes: a plurality of domain wall moving elements; a first wiring which is electrically connected to a reference potential and is electrically connected to at least one domain wall moving element of the plurality of domain wall moving elements; a second wiring which is electrically connected to at least two or more domain wall moving elements of the plurality of domain wall moving elements; a first switching element which is connected between each of the domain wall moving elements and the first wiring; and a second switching element which is connected between each of the domain wall moving elements and the second wiring, wherein an OFF resistance of the first switching element is smaller than an OFF resistance of the second switching element.

A magnetic recording array includes: a plurality of domain wall moving elements; a first wiring which is electrically connected to a reference potential and is electrically connected to at least one domain wall moving element of the plurality of domain wall moving elements; a second wiring which is electrically connected to at least two or more domain wall moving elements of the plurality of domain wall moving elements; a first switching element which is connected between each of the domain wall moving elements and the first wiring; and a second switching element which is connected between each of the domain wall moving elements and the second wiring, wherein an OFF resistance of the first switching element is smaller than an OFF resistance of the second switching element.

A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

Discussed herein are systems and methods for protecting against transistor degradation in a high-voltage (HV) shifter to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises memory cells and a HV shifter circuit that includes a signal transfer circuit, and first and second HV control circuits. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The first HV control circuit couples a bias voltage to the P-channel transistor for a first time period, and the second HV control circuit couples a stress-relief signal to the P-channel transistor for a second time period, after the first time period, to reduce degradation of the P-channel transistor. The transferred high voltage can be used to charge the access line to selectively read, program, or erase memory cells.

A magnetic recording array includes: a plurality of domain wall moving elements; a first wiring which is electrically connected to a reference potential and is electrically connected to at least one domain wall moving element of the plurality of domain wall moving elements; a second wiring which is electrically connected to at least two or more domain wall moving elements of the plurality of domain wall moving elements; a first switching element which is connected between each of the domain wall moving elements and the first wiring; and a second switching element which is connected between each of the domain wall moving elements and the second wiring, wherein an OFF resistance of the first switching element is smaller than an OFF resistance of the second switching element.

A magnetic recording array includes: a plurality of domain wall moving elements; a first wiring which is electrically connected to a reference potential and is electrically connected to at least one domain wall moving element of the plurality of domain wall moving elements; a second wiring which is electrically connected to at least two or more domain wall moving elements of the plurality of domain wall moving elements; a first switching element which is connected between each of the domain wall moving elements and the first wiring; and a second switching element which is connected between each of the domain wall moving elements and the second wiring, wherein an OFF resistance of the first switching element is smaller than an OFF resistance of the second switching element.

The objective of the invention is to provide technology allowing data taking a plurality of values to be transmitted and received using one set of coils when sending data through TCI technology using magnetic field coupling. This layered semiconductor device has at least a first semiconductor chip and a second semiconductor chip layered therein, the first semiconductor chip transmitting data in a contactless manner, and the second semiconductor chip receiving, in a contactless manner, the data that has been transmitted. The first semiconductor chip contains: a transmission unit outputting a transmission signal that may acquire, on the basis of the value of the data to be sent, at least 3 types of states representing the value of the data; and a transmission coil converting the transmission signal into a magnetic field signal. The second semiconductor chip contains: a reception coil whereby the magnetic field signal converted by the transmission coil is converted into a reception signal; and a reception unit reconstructing, on the basis of the state of the reception signal, the data that has been transmitted.

A magnetic recording array includes: a plurality of domain wall moving elements; a first wiring which is electrically connected to a reference potential and is electrically connected to at least one domain wall moving element of the plurality of domain wall moving elements; a second wiring which is electrically connected to at least two or more domain wall moving elements of the plurality of domain wall moving elements; a first switching element which is connected between each of the domain wall moving elements and the first wiring; and a second switching element which is connected between each of the domain wall moving elements and the second wiring, wherein an OFF resistance of the first switching element is smaller than an OFF resistance of the second switching element.

A magnetic recording array includes: a plurality of domain wall moving elements; a first wiring which is electrically connected to a reference potential and is electrically connected to at least one domain wall moving element of the plurality of domain wall moving elements; a second wiring which is electrically connected to at least two or more domain wall moving elements of the plurality of domain wall moving elements; a first switching element which is connected between each of the domain wall moving elements and the first wiring; and a second switching element which is connected between each of the domain wall moving elements and the second wiring, wherein an OFF resistance of the first switching element is smaller than an OFF resistance of the second switching element.