A semiconductor device capable of changing a data programming process in a simple manner according to a situation is provided. The semiconductor device includes a plurality of memory cells, a programming circuit for supplying a programming current to the memory cell, and a power supply circuit for supplying power to the programming circuit. The power supply circuit includes a charge pump circuit for boosting the external power supply, a voltage of the external power supply according to the selection indication, and a selectable circuit capable of switching the boosted voltage boosted by the charge pump circuit. The control circuit further includes a control circuit for executing data programming processing by the programming circuit by switching the selection indication.

A memory device including a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit is configured to generate a plurality of operating voltages used in a memory operation, based on a target pump clock, and perform the memory operation by using the plurality of operating voltages. The control logic is configured to select the target pump clock among a plurality of pump clocks, based on a number of data bits which selected memory cells on which the memory operation is to be performed among the plurality of memory cells store, and control the peripheral circuit to perform the memory operation on the selected memory cells.

Provided is a method for executing a security related process comprising at least a first operation and a subsequent programming operation of a memory area in a first memory row of a first memory of a system and using as input security data stored in said second memory of said system, wherein said first memory is a non-volatile memory and said system comprises a first memory charge pump. The method comprises, when the execution of said security related process is triggered: opening (S2) the first memory row, charging (S3) said first memory charge pump, performing (S4) said first operations of the security related process, based on said security data from the second memory, and performing (S5) said programming operation of said memory area in said opened first memory row using said charged charge pump.

A memory device can include a nonvolatile memory (NVM) cell array, data path circuits, coupled between the NVM cell array and an output of the device, that are configured to enable access to the NVM cell array via a plurality of bit lines. A first charge pump can generate a first voltage supply. A second charge pump can generate a second voltage supply. Switch circuits are configured to, in a first mode, couple the first voltage supply to data path circuits, and in a second mode, couple the second voltage supply to the data path circuits. The first charge pump, the second charge pump, the switch circuits, the data path circuits and the NVM cell array are formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.

A voltage detection circuit and a charge pump circuit using the voltage detection circuit are provided. The voltage detection circuit includes: a voltage raising circuit configured to adjust a voltage to be measured and then output an adjusted voltage, where the adjusted voltage is equal to the sum of the voltage to be measured and a reference voltage; and the reference voltage is generated by a combination of a first voltage with a positive temperature coefficient and a second voltage with a negative temperature coefficient.

The present disclosure describes embodiments of a memory system with a memory cell power supply. The memory system can include a circuit with a first voltage supply, a second voltage supply, pull-up devices, pull-down devices, and pass devices. The first voltage supply is configured to provide a first voltage. The first voltage supply is configured to apply the first voltage to gate terminals of the pass devices. The second voltage supply is electrically coupled to S/D terminals of the pull-up devices and is configured to transition from the first voltage to the second voltage for a read operation.

A power supply circuit and a memory are provided. The power supply circuit includes a voltage source, multiple power supply circuits and a control circuit. The multiple power supply circuits are connected to the voltage source. If the voltage source is effective and the multiple power supply circuits are in an enable state, a voltage of a power supply terminal is pulled up to a preset voltage, and power is supplied to the load units during the pulling up process. A first-type power circuit enters the enable state if a first enable signal is received, and each of second-type power supply circuits enters the enable state if second enable signal is received.

A variety of applications can include apparatus or methods that provide a well ring for resistive ground power domain segregation. The well ring can be implemented as a n-well in a p-type substrate. Resistive separation between ground domains can be generated by biasing a n-well ring to an external supply voltage. This approach can provide a procedure, from a process standpoint, that provides relatively high flexibility to design for chip floor planning and simulation, while providing sufficient noise rejection between independent ground power domains when correctly sized. Significant noise rejection between ground power domains can be attained.

A memory module includes a module substrate, a plurality of memory devices, a first power line, and a second power line. The memory devices are mounted on the module substrate. Each of the memory devices includes a power management member. The first power line may be arranged in the module substrate to provide each of the memory devices with power. The second power line may be electrically connected between the power management members of adjacent memory devices to control and share the power provided to the adjacent memory devices.

In an embodiment, an apparatus is disclosed that includes a power management integrated circuit (PMIC). The PMIC includes a voltage regulator supplied by a first power source and configured to generate a first output and a charge pump supplied by a second power source and configured to generate a second output. A bias voltage output of the power management integrated circuit is generated based at least in part on the first output and the second output. The charge pump is configured to adjust the second output based at least in part on a comparison between the bias voltage output and a reference voltage.