Techniques for providing temperature trim codes to multiple reference circuits of an integrated circuit are provided. In an example, a string of primary latch circuits can provide a set of pre-defined temperature trim codes to a multiplexer in response to a token of a series of tokens. The multiplexer can provide two trim of the trim codes to an interpolator based on a temperature reading of the integrated circuit. The interpolator can provide an interpolated trim code and the trim code can be distributed to a reference circuit based on the token.

A memory system includes a connector through which power for the memory system is to be supplied from an external device, a controller, a nonvolatile memory device, a power source circuit connected to the controller and the nonvolatile memory device by power lines through which power is supplied to the controller and the nonvolatile memory device, and a power source control circuit that receives a supply of power from the external device through the connector and supplies the power to the power control circuit. The power source control circuit is configured to detect using a divided voltage of a voltage of the power supplied thereto, that the voltage of the power supplied thereto is higher than a predetermined voltage and interrupt the power supplied to the power control circuit if the voltage of the power supplied thereto is higher than the predetermined voltage.

One or more sampling parameters of an application associated with a downstream voltage regulator may be determined. A power supply rejection ratio (“PSRR”) and a switching frequency of an upstream voltage regulator may be dynamically adjusted based on the sampling parameters of the application associated with the downstream voltage regulator. The sampling parameters may include a noise level and a workload of the selected application.

Methods, systems, and devices related to an improved driver for non-binary signaling are described. A driver for a signal line may include a set of drivers of a first type and a set of drivers of a second type. When the driver drives the signal line using multiple drivers of the first type, at least one additional driver of the first type may compensate for non-linearities associated with one or more other drivers of the first type, which may have been calibrated at other voltages. The at least one additional driver of the first type may be calibrated for use at a particular voltage, to compensate for non-linearities associated with the one or more other drivers of the first type as exhibited at that particular voltage.

In an example, a multiplexer is provided. The multiplexer may include one or more first strings controlling access to source-lines of the memory, wherein a first string of the one or more first strings includes a first set of two high voltage transistors and a first plurality of low voltage transistors. The multiplexer may include one or more second strings controlling access to bit-lines of the memory, wherein a second string of the one or more second strings includes a second set of two high voltage transistors and a second plurality of low voltage transistors. A method for operating such multiplexer is provided.

A supply voltage sensitivity of an output current of a bias current generator circuit is reduced. The bias current generator includes a plurality of transistors and a plurality of resistors coupled to the plurality of transistors. The supply voltage sensitivity of the output current of the bias current generator circuit is reduced by applying a second bias current generated by the bias current generator circuit to a first bias current generated by the bias current generator circuit.

A storage apparatus includes a control chip, a storage chip, a power interface configured to receive a first voltage, a first variable-voltage circuit. An input end of the first variable-voltage circuit is coupled to the power interface. The first variable-voltage circuit is configured to convert the first voltage into a second voltage, and provide the second voltage to the control chip and a second variable-voltage circuit, where an input end of the second variable-voltage circuit is coupled to the power interface. The second variable-voltage circuit is configured to convert the first voltage into a third voltage and provide the third voltage to the control chip and the storage chip.

A system includes: a high bandwidth memory (HBM) including a first sensing unit configured to generate one or more first environmental signals corresponding to a first transistor in a first memory cell, and a second sensing unit configured to generate one or more second environmental signals corresponding to a second transistor in a second memory cell; and a differentiated dynamic voltage and frequency scaling (DDVFS) device configured to perform the following (1) for a first set of the memory cells which includes the first memory cell, controlling temperature by adjusting one or more first transistor-temperature-affecting (TTA) parameters of the first set based on the one or more first environmental signals, and (2) for a second set of the memory cells which includes the second memory cell, controlling temperature by adjusting one or more second TTA parameters of the second set based on the one or more second environmental signals.

Embodiments relate to improving the biasing of active electronic components such as, for example, sense amplifiers. Embodiments include an adjustable bias signal generator that receives a reference signal as an input and generates a corresponding bias signal as an output. The adjustable bias signal generator may comprise a voltage driver and capacitor divider circuitry. In some embodiments, the capacitor divider circuitry is configurable by selecting specific capacitor dividers using a digital code. In other embodiments, the voltage driver is adjustable by applying different trim settings to tune the output of the voltage driver. The voltage driver may be temperature compensated by multiplexing different trim settings that correspond to different temperatures.

Disclosed is a user system which includes a first device and a second device, which share a shared voltage, and a power management integrated circuit (PMIC) generating the shared voltage. An operation method of the user system includes performing a first operation of the first device, determining whether a second operation of the second device is to be performed while the first device performs the first operation, based on an operation profile, and when it is determined that the second operation of the second device is to be performed while the first device performs the first operation, changing a power mode of the PMIC from a first power mode to a second power mode, before the second device performs the second operation. The PMIC generates the shared voltage based on the first power mode or the second power mode.