A system for dual mode operation having power saving and active modes in a stacked circuit topology having logic preservation is provided. The system includes a pre-charge circuit and a sleep mode control circuit for providing a signal to disable a plurality of circuit elements and switching a mode of the system, the sleep mode control circuit being coupled to the pre-charge circuit and further being coupled to a logic function circuit, wherein the plurality of circuit elements comprise logic gates and transistor devices. The system also includes a keeper circuit coupled to the global bitline, and the logic function circuit coupled to a solar bitline, wherein the logic function circuit preserves a state of the solar bitline, the state of the global bitline determines the state of the solar bitline. The system includes an effective pull-up transistor coupled to the sleep mode control circuit and the logic function circuit.

A semiconductor device and a power-off method of the semiconductor device, the semiconductor device including a first power source group including first and second power sources, a second power source group including a third power source and a power sequence controller. The power sequence controller performs power-on operations and power-off operations of the first to third power sources. The power sequence controller starts a power-off operation of the first power source group at a first time, and starts a power-off operation of the second power source group when the power voltage of the first power source group becomes a first voltage or when a first reference time has passed from the first time.

Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.

1. The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.

Provided are electronic devices and methods for power reduction in systems with multiple memory ranks. The electronic device includes a memory system including first and second memory ranks and a memory controller connected to the memory system and configured to control power of the memory system. The memory controller being configured to cause the first memory rank to enter an idle power down (IPD) state during memory access in which a data toggle time without a data bubble is equal to or greater than an IPD minimum gain duration in another bank access for the second memory rank.

A control circuit includes a bias circuit. The bias circuit is configured to provide a bias current for a functional circuit. The bias circuit includes a first bias circuit and a second bias circuit. The first bias circuit is configured to provide a first bias current, and the second bias circuit is configured to provide a second bias current. Herein, the first bias current is smaller than the second bias current, the first bias circuit is configured to be in a normally open state after being powered on, and the second bias circuit is configured to receive a bias enabling signal and provide the second bias current based on the bias enabling signal.

A semiconductor device includes a memory mat having: a plurality of memory cells; a sense amplifier connected to a memory cell selected from the plurality of memory cells; a first power supply wiring; a first switch connected between the sense amplifier and the first power supply wiring and made an ON state in operating the sense amplifier; and a second switch connected to the sense amplifier and made an ON state in operating the sense amplifier, a second power supply wiring arranged outside the memory mat and connected to the first power supply wiring, a third power supply wiring arranged outside the memory mat and connected to the sense amplifier via the second switch, and a short switch arranged outside the memory mat and connected between the second and third power supply wirings. Here, in operating the sense amplifier, the short switch is made an ON state.

The present invention provides a power control circuit and control method. The power control circuit includes: a control module configured to control, according to an activation command, a memory bank of a plurality of memory banks to perform an operation; a power management module configured to wake up a local power supply for the memory bank according to a clock enable signal; and a power control module communicatively coupled with the power management module and configured to: send the clock enable signal to the power management module of the memory bank corresponding to the activation command in a power-saving mode; and send the clock enable signal to power management modules of the plurality of memory banks in a non-power-saving mode, where the power-saving mode indicates that a system clock is in a low-frequency state.

Methods, systems, and devices for memory device operation are described. A memory device may operate in different modes in response to various conditions and user constraints. Such modes may include a power-saving or low power mode. While in the low power mode, the memory device may refrain from operations, such as self-refresh operations, on one or more of the memory array(s) included in the memory device. The memory device may deactivate external interface components and components that may generate operating voltages for the memory array(s), while the memory device may continue to power circuits that store operating information for the memory device. The memory device may employ similar techniques in other operating modes to accommodate or react to different conditions or user constraints.

Systems and methods are disclosed, including rebuilding a logical-to-physical (L2P) data structure of a storage system subsequent to relocating assigned marginal group of memory cells of a memory array of the storage system, such as when resuming operation from a low-power state, including an asynchronous power loss (APL).