The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.

A semiconductor memory device includes a memory cell array, a memory apparatus and a power-on operation apparatus, and is capable of knowing whether a reading of the setting information which is set during the power-on operation had been completed correctly or not. The flash memory reads the fuse memory when it is detected that the power supply has reached the power-on detection level, and determines whether the reading of the fuse memory had been completed correctly. When not completed correctly, the fuse memory is read again within the maximum read count, and the setting information (which was read from the fuse memory) is written into the CF register. The identification information (that identifies whether the reading of the fuse memory has been completed correctly or not) is stored in the register.

Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

A voltage detecting circuit for a non-volatile memory is provided. When a standby signal is not asserted, a power supply unit of the non-volatile memory provides an array voltage to a first node. The voltage detecting circuit includes an initial voltage generator, a capacitor, a latch and a combinational logic circuit. The initial voltage generator receives an inverted standby signal and an enable signal. An output terminal of the initial voltage generator is connected with a second node. The capacitor is coupled between the first node and the second node. An input terminal of the latch is connected with the second node. An output terminal of the latch is connected with a third node. An input terminal of the combinational logic circuit is connected with the third node. An output terminal of the combinational logic circuit generates the enable signal.

Disclosed is a user system which includes a first device and a second device, which share a shared voltage, and a power management integrated circuit (PMIC) generating the shared voltage. An operation method of the user system includes performing a first operation of the first device, determining whether a second operation of the second device is to be performed while the first device performs the first operation, based on an operation profile, and when it is determined that the second operation of the second device is to be performed while the first device performs the first operation, changing a power mode of the PMIC from a first power mode to a second power mode, before the second device performs the second operation. The PMIC generates the shared voltage based on the first power mode or the second power mode.

An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to detect a power-up state of the memory device following a power loss event; detect a read error with respect to data residing in a block of the memory device, wherein the block is associated with a current voltage offset bin; and perform temporal voltage shift (TVS)-oriented calibration for associating the block with a new voltage offset bin.

The operation speed of a semiconductor device is improved. The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length-channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.

A circuit for monitoring an output voltage of a voltage supply is shown. The circuit comprises a microcontroller for controlling a system, a shift register and a diagnostic circuit. The microcontroller has an input for receiving serial output data of the shift register, wherein the input is connected to the serial output of the shift register. The diagnostic circuit is designed to diagnose the voltage supply and has a diagnostic output which is connected to a data input of the shift register for inputting a diagnostic bit.

A memory device that is operable at a first voltage domain and a second voltage domain includes a memory array, a power saving mode pin and a word line level shifter circuit. The memory array operates at the first voltage domain. The power saving mode pin is configured to receive a power saving mode enable signal that is at the second voltage domain. The power saving mode enable signal is configured to enable a power saving mode of the memory device. The word line level shifter circuit is coupled to the memory array and the power saving mode pin, and is configured to clamp a word line of the memory array to a predetermined voltage level that corresponds to a first logic state during the power saving mode of the memory device.

Methods, systems, and devices for a dynamic interval for entering a low power state are described. A memory system or device may support a low power mode, which the memory system or device may enter in response to a command from a host system. In some cases, an amount of idle time observed by the host system before issuing such a command may vary based on a status of maintenance operations for the memory system or device. Additionally or alternatively, after receiving such a command, the memory system or device may complete one or more pending maintenance operations before entering the low power mode.