In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.

An apparatus includes a voltage regulator coupled with a first voltage source, which supplies core memory circuitry. A first transistor is coupled between an output of the voltage regulator and input/output (I/O) circuitry. A second transistor is coupled between a second voltage source and the I/O circuitry, the second voltage source to power a set of I/O buffers. Control logic coupled with gates of the first and second transistors is to perform operations including: causing the second transistor to be activated to permit current to flow from the second voltage source to the I/O circuitry; in response to detecting a current draw from the I/O circuitry that satisfies a first threshold criterion, causing the first transistor to be activated; and causing the second transistor to be deactivated over a time interval during which the I/O circuitry is powered by the first voltage source and the second voltage source.

Logical memory is divided into two regions. Data in the first region is always retained. The first region of memory is designated online (or powered on) and is not offlined during standby or low power mode. The second region is the rest of the memory which can be potentially placed in non-self-refresh mode during standby by offlining the memory region. Content in the second region can be moved to the first region or can be flushed to another memory managed by the operating system. When the first region does not have enough space to accommodate data from the second region, the operating system can increase the logical size of the first region. Retaining the content of the first region by putting that region in self-refresh and saving power in the second region by not putting it in self-refresh is performed by an improved Partial Array Self Refresh scheme.

A semiconductor device includes a clock gating circuit and a control circuit. The clock gating circuit outputs a gated clock signal based on a clock signal. Transitions of the clock signal are output in the gated clock signal in response to a clock enable signal having an enable value and are disabled from being output in the gated clock signal in response to the clock enable signal having a disable value. The control circuit includes a first portion that operates based on the clock signal. The first portion sets the clock enable signal to the disable value in response to a disable control and sets the clock enable signal to the enable value in response to a wakeup control. The control circuit includes a second portion that operates based on the gated clock signal. The second portion provides the disable control to the first portion during an operation.

Systems and methods for injecting a toggling signal in a command pipeline configured to receive a multiple command types for the memory device. Toggling circuitry is configured to inject the toggling signal into at least a portion of the command pipeline when the memory device is in a power saving mode and the command pipeline is clear of valid commands. The toggling is blocked from causing writes by disabling a data strobe when a command that is invalid in the power saving mode is asserted during the power saving mode.

System on a Chip (SoC) integrated circuits are configured to reduce Static Random-Access Memory (SRAM) power leakage. For example, SoCs configured to reduce SRAM power leakage may form part of an artificial reality system including at least one head mounted display. Power switching logic on the SoC includes a first power gating transistor that supplies a first, higher voltage to an SRAM array when the SRAM array is in an active state, and a third power gating transistor that isolates a second power gating transistor from the first, higher voltage when the SRAM array is in the active state. The second power gating transistor further supplies a second, lower voltage to the SRAM array when the SRAM array is in a deep retention state, such that SRAM power leakage is reduced in the deep retention state.

A chip includes a processor, a memory, and a storage controller of the memory. There is an access path between the processor and the storage controller, and the processor reads data from or writes data into the memory by using the storage controller through the access path. The chip further includes a shielding circuit. The shielding circuit is configured to shield a signal on the access path when the processor is powered off.

A method and apparatus are for monitoring a secondary power device and for accurately checking a state of the secondary power device, and an electronic system includes the apparatus. The method of monitoring a secondary power device includes setting a first reference parameter by using a voltage of at least one capacitor of the secondary power device, setting a second reference parameter by using the voltage of the at least one capacitor and the first reference parameter, and setting a reference level for checking of the state of the secondary power device by using the second reference parameter, wherein the reference level is used in checking of the state of the secondary power device.

A latch circuit device includes: a latch circuit configured to latch an input signal to a microcomputer; a detection circuit configured to detect that the input signal is input to the latch circuit during a sleep period in which the microcomputer is in a sleep state; a wake-up circuit configured to transmit a wake-up signal to the microcomputer when an input of the input signal is detected during the sleep period; a sampling circuit configured to read the input signal from the latch circuit; a transmission circuit configured to transmit the input signal read by the sampling circuit to the microcomputer returned from the sleep state based on the wake-up signal; and a release circuit configured to release a latch state of the latch circuit after the input signal is read.

A semiconductor device including an error amplifier configured to receive a voltage of an output node and a reference voltage, a flipped voltage follower (FVF) circuit configured to receive an output of the error amplifier and maintain the voltage of the output node at the reference voltage, and a bias current control circuit configured to receive first to third mode signals, control a magnitude of a bias current flowing through the FVF circuit based on the first to third mode signals, control the bias current of a first magnitude, based on the first mode signal, control the bias current of a second magnitude smaller than the first magnitude, based on the second mode signal, and control the bias current of a third magnitude smaller than the second magnitude, based on the third mode signal.