Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

The present disclosure provides a signal line structure, a signal line driving method, and a signal line circuit. The signal line structure includes a plurality of parallel signal lines, where each of the signal lines is maintained in a drive state at any time.

A memory device that uses different programming parameters base on the word line(s) to be programmed is described. The programming parameter PROGSRC_PCH provides a pre-charge voltage to physical word lines. In some instances, the PROGSRC_PCH voltage is decoupled, and a new PROGSRC_PCH represents an adjusted (e.g., increased) pre-charge voltage for a certain physical word line or word line zone (i.e., predetermined group of word lines). Using different PROGSRC_PCH voltages can limit or prevent Vt distribution window degradation, particularly for relatively low physical word lines. Additionally, the overall programming time and average current consumed can also be reduced.

A memory device that operates at high speed is provided. The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.

A semiconductor device may implement a command-over-data function on a multi-level signaling data bus architectures. The multi-level signaling data bus architecture may support a multi-level communication architecture that includes a plurality of channels each including conversion of M bitstreams to N multi-level signals, where M is greater than N. A bitstream includes a plurality of bits provided serially, with each bit of the bitstream provided over a period of time. The multi-level signaling data bus is adapted to transmit data using a first set of assigned states of the data bus, and to transmit commands using at least a second assigned state of the data bus.

Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

A computing system architecture is presented for decoupling execution of workload by crossbar arrays and similar memory modules. The computing system includes: a data bus; a core controller connected to the data bus; and a plurality of local tiles connected to the data bus. Each local tile in the plurality of local tiles includes a local controller and at least one memory module, where the memory module performs computation using the data stored in memory without reading the data out of the memory.

A memory device includes a pair of memory cells, an analog-to-digital converter (ADC), and a processing circuit. The pair of memory cells has a first memory cell and a second memory cell. The ADC, having a first input terminal and a second input terminal, is configured to convert a first data signal at the first input terminal and a second data signal at the second input terminal into a digital output indicating a data value associated with a particular state stored in the pair of memory cells. The processing circuit, coupled to a storage node of the first memory cell, a storage node of the second memory cell, and the first and the second input terminals, is configured to selectively adjust the first data signal and the second data signal according to first data stored in the first memory cell and second data stored in the second memory cell.

A semiconductor component for a memory device is provided. The semiconductor component comprises a first active region extending in a first direction; a second active region extending in the first direction; a first conductive layer disposed across the first active region and the second active region, in a second direction substantially perpendicular to the first direction; a second conductive layer extending in the first direction; and a first conductive via connecting the first conductive layer and the second conductive layer.