A memory controller for accessing a memory, comprises a holding circuit which holds a plurality of read or write access requests from a bus master, a read/write control circuit which selects one of the access requests in the holding circuit and issues a read command or a write command; and an active control circuit which selects the access request held in the holding circuit and issues an active command, wherein the active control circuit includes a generation circuit that generates number of activated read commands and number of activated write commands, and a selection circuit that, when the number of activated read commands is not less a threshold, issues the active command of an read access, and when the number of activated write commands is not less than the threshold, issues the active command of a write access.

A control circuit, a method for reading and writing and a memory are provided. The control circuit includes a pre-charge circuit, an amplification circuit and an equalization circuit. The pre-charge circuit is directly electrically connected to at least one of a bit line or a complementary bit line. The amplification circuit has a first node and a second node. The equalization circuit is connected between the first node and the bit line and between the second node and the complementary bit line.

The present disclosure provides buffer circuits of 3D NAND memory device. In some embodiments, the buffer circuit comprises a first bit line segment sensing branch connected to a first bit line segment and including a low-voltage latch, and a second bit line segment sensing branch connected to a second bit line segment and including a sensing latch. The first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit.

The present disclosure provides page buffer circuits of 3D NAND devices. In some embodiments, the page buffer circuit comprises a first bit line segment sensing branch connected to a first bit line segment of a bit line, and a second bit line segment sensing branch connected to a second bit line segment of the bit line. The first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit. In some embodiments, the first bit line segment sensing branch comprises a first sense latch and a first bit line pre-charge path, and the second bit line segment sensing branch comprises a second sense latch and a second bit line pre-charge path.

A read/write switching circuit and a memory are provided. The read/write switching circuit includes: a first data line (Ldat) connected to a bit line (BL) through a column select module, a first complementary data line (Ldat #) connected to a complementary bit line through the column select module, a second data line (Gdat) and a second complementary data line (Gdat #), and further includes: a read/write switching module (101) configured to transmit data between the first data line and the second data line and transmit data between the first complementary data line (Ldat #) and the second complementary data line (Gdat #) during read and write operations in response to read and write control signals; and an amplification module (102) connected between the first data line (Ldat) and the first complementary data line (Ldat #) and configured to amplify data of the first data line (Ldat) and data of the first complementary data line (Ldat #).

Methods of operating a memory device are disclosed. A method may include receiving a write command, and in response to the write command, performing a write operation without precharging a local input/output line subsequent to receipt of the write command and prior to performing the write operation. Another method may include receiving a read command, performing a read operation in response to the read command, and receiving an additional command without precharging the local input/output line subsequent to performing the read operation and prior to receiving the additional command. Memory devices and systems are also disclosed.

A data storage includes a memory array including a plurality of memory cells, and peripheral circuitry disposed underneath the memory array. The peripheral circuitry includes an M-tier sense amplifier (SA) circuit including X stacks of SA latches, wherein each SA latch is respectively coupled to a bit line of a memory cell of the plurality of memory cells; and an N-tier memory cache data (XDL) circuit including Y stacks of XDL latches, wherein M is less than N, and X is greater than Y. The peripheral circuitry further includes data path circuitry coupling (i) each SA latch of the X stacks of SA latches to (ii) a respective XDL latch of the Y stacks of XDL latches.

The present disclosure includes apparatuses and methods for partitioned parallel data movement. An example apparatus includes a memory device that includes a plurality of partitions, where each partition of the plurality of partitions includes a subset of a plurality of subarrays of memory cells. The memory device also includes sensing circuitry coupled to the plurality of subarrays, the sensing circuitry including a sense amplifier. A controller for the memory device is configured to direct a first data movement within a first partition of the plurality of partitions in parallel with a second data movement within a second partition of the plurality of partitions.

The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.

Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are coupled to sense lines. The apparatus can include a controller configured to control a sensing circuitry, that is coupled to the sense lines, to perform a number of operations without transferring data via an input/output (I/O) lines. The sensing circuitry can be controlled to calculate an error code for data stored in the array of memory cells and compare the error code with an initial error code for the data to determine whether the data has been modified.