Memory devices are disclosed. A memory device may include a command and address (CA) interface region including a first CA input circuit configured to generate a first CA output AND a second CA input circuit configured to generate a second CA output. The first CA input circuit and the second CA input circuit are arranged in a mirror relationship. The CA interface region further includes a swap circuit configured to select one of the first CA output and the second CA output for a first internal CA signal and select the other of the first CA output and the second CA output for a second internal CA signal. Memory systems and systems are also disclosed.

A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.

Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.

A page buffer includes a charging circuit, first and second storage circuits, and a selection circuit. The charging circuit charges a bit line during a precharging period. The first storage circuit determines and stores data corresponding to a state of a selected memory cell among memory cells connected to the bit line while the charging circuit charges the bit line. The second storage circuit, which is a circuit separate from the first storage circuit, determines and stores data corresponding to a state of the selected memory cell after the precharging period. The selection circuit outputs a control voltage controlling a switch element connected between the bit line and the charging circuit, and determines a magnitude of the control voltage during the precharging period, based on the data stored in the first storage circuit.

A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.

Provided are a signal generation circuit and a memory. The signal generation circuit includes: a clock delay circuit for delaying an initial pulse signal to output an intermediate signal delayed by a first delay duration, the first delay duration being equal to one or more clock cycles; a physical delay circuit for delaying the intermediate signal to output a target signal, if an actual delay duration of the physical delay circuit is equal to a second delay duration, the target signal being delayed by a target duration, a difference between the actual and second delay durations fluctuating within a first preset range, and the shorter the second delay duration, the narrower the first preset range; and a generation circuit for outputting a function pulse signal having a pulse width equal to a time interval between rising edges of the initial pulse signal and the target signal.

There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

A data receiving circuit includes: a first amplification module configured to receive a data signal and a reference signal, compare the data signal and the reference signal in response to a first sampling clock signal, and output a first voltage signal and a second voltage signal; a decision feedback control module configured to generate a second sampling clock signal in response to the enable signal; a decision feedback equalization module configured to, when the enable signal is in a first level value interval, perform decision feedback equalization in response to the second sampling clock signal and stop performing the decision feedback equalization when the enable signal is in a second level value interval; and a second amplification module configured to process the first voltage signal and the second voltage signal and output the first output signal and the second output signal.

Fuses can store different delay states to cause execution of a command to be staggered for different memory dies of a memory package. Fuse arrays can be included in the memory package and programmed to cause execution of a command to be delayed by different amounts for different dies. The fuse arrays can be fabricated and then programmed to cause different delays for different dies.

Methods for improving timing in memory devices are disclosed. A method may include sampling a command signal according to a clock signal to obtain standard-timing commands. The method may also include sampling the command signal according to an adjusted clock signal to obtain time-adjusted commands. The method may also include comparing the standard-timing commands and the time-adjusted commands. The method may also include determining an improved timing for the clock signal based on the comparison of the standard-timing commands and the time-adjusted commands. The method may also include adjusting the clock signal based on the improved timing. Associated systems and methods are also disclosed.