A system includes a mixer of a phase interpolator. The mixer includes a dynamic load whose output signal is coupled to a subsequent stage of the phase interpolator. The dynamic load is configured to provide an alternating current (AC) signal to the subsequent stage of the phase interpolator as input clock signals. The mixer further includes a static load whose output signal is coupled to the subsequent stage of the phase interpolator in parallel with the respective output signal line of the dynamic load. The static load configured to provide a direct current (DC) signal to the phase interpolator temporarily in replacement of the respective AC signals to prevent output signals of the subsequent stage of the phase interpolator from being unpredictable.

A clock signal processing circuit includes a clock buffer configured to generate a pair of second clock signals with opposite phases after receiving a pair of first clock signals with opposite phases and configured to fix the second clock signals to determined levels according to a control signal until toggling of the first clock signals begins.

Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

A signal processing circuit includes a delay locked loop (DLL) circuit, a data output path circuit, and a first phase detector circuit. The DLL circuit is arranged to receive a memory clock signal, and generate a DLL output signal according to the memory clock signal and a DLL feedback signal. The data output path circuit is coupled to the DLL circuit, and is arranged to generate a DQS signal according to the DLL output signal. The first phase detector circuit is coupled to the data output path circuit, and is arranged to receive the memory clock signal and the DQS signal, and detect a phase difference between the memory clock signal and the DQS signal to generate a first phase detection result.

Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

Systems and methods for gating, via clock gating circuitry, a clock signal based at least in part on a mode register value indicative of synchronization of a command address signal with the clock signal when the mode register value indicates synchronization of the command address signal with the clock signal has not occurred. The clock gating circuitry is configured to, gate the clock signal based at least in part on the mode register value and a chip select signal value when the mode register value indicates synchronization of the command address signal with the clock signal has occurred.

Memory devices and methods of operating memory devices in which maintenance operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., operations in excess of a predetermined threshold) warrants a maintenance operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of operations at the memory location, to schedule a maintenance operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled maintenance operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further operations at the memory location until after the count has been decreased.

A semiconductor device includes a pre-pulse generation circuit configured to generate a pre-pulse, based on a write shifting pulse and a write leveling activation signal; a write control signal generation circuit configured to generate a write control signal, based on the pre-pulse and a division clock; and a write leveling control circuit configured to generate detection data including information on a phase difference between a data clock and a system clock, based on the pre-pulse and the division clock.

A clock signal processing circuit includes a clock buffer configured to generate a pair of second clock signals with opposite phases after receiving a pair of first clock signals with opposite phases and configured to fix the second clock signals to determined levels according to a control signal until toggling of the first clock signals begins.

A semiconductor device may include a division control circuit and a latch circuit. The division control circuit may be configured to divide an external clock to generate a first preliminary divided clock and a second preliminary divided clock. The division control circuit may be configured to output the first and second preliminary divided clocks or any one of the first and second preliminary divided clocks as first and second divided clocks. The latch circuit may be configured to latch an external control signal in response to the first and second divided clocks and configured to output latched signals as first and second latch control signals.