A memory is provided that includes a self-timed memory circuit that controls the isolation of a sense amplifier from a column selected by a column multiplexer until the completion of a bit line voltage difference development delay. The self-timed memory circuit also controls the release of a pre-charge for the sense amplifier responsive to the completion of the bit line voltage difference development delay.

A compute-in-memory array is provided that implements a filter for a layer in a neural network. The filter multiplies a plurality of activation bits by a plurality of filter weight bits for each channel in a plurality of channels through a charge accumulation from a plurality of capacitors. The accumulated charge is digitized to provide the output of the filter.

A device is provided. The device includes multiple transistors, a first sense circuit, and a precharge circuit. The transistors are coupled to a tracking bit line and configured to generate a first tracking signal. The first sense circuit is configured to generate a first sense tracking signal in response to the first tracking signal. The precharge circuit is configured to generate, in response to a rising edge and a falling edge of the first sense tracking signal, a precharge signal for precharging data lines.

Embodiments herein relate to optimizing the duration of a sense amp enable signal in a memory device such as SRAM. A control circuit asserts the sense amp enable signal in response to a clock signal from a replica column of the SRAM. A feedback path extends from the sense amps back to the control circuit. In one approach, a change in a feedback signal on the feedback path indicates the sense amps have all received the sense amp enable signal. In another approach, a change in a feedback signal on the feedback path indicates the sense amps have all completed their sensing operations. In some cases, a selection can be made among multiple feedback paths.

A memory system includes a substrate, a first memory package mounted on the substrate and including a plurality of first non-volatile memories (NVMs), a second memory package mounted on the substrate and including a plurality of second NVMs, and a memory controller configured to increase performance of at least one of the plurality of first NVMs and lower performance of at least one of the plurality of second NVMs, based on a temperature of the substrate.

A memory device is disclosed. The memory device includes word lines, a tracking bit line and a word line driver. The word lines are configured to transmit word line signals to memory cells. The tracking bit line is coupled to a first plurality of tracking cells that are arranged in rows. The word line driver is coupled to the word lines and a control circuit that is coupled through the tracking bit line to the word lines. The word line driver is configured to control a falling edge of each of the word line signals, by receiving each corresponding tracking bit line signal of tracking bit line signals transmitted from the tracking bit line, based on a resistance of a length of the tracking bit line. The length is substantially distanced from each corresponding row of the rows to the control circuit. A method is also disclosed herein.

In some embodiments, an apparatus comprises: a static random access memory (SRAM) device. The SRAM device may have a bit cell array comprising a plurality of bit cells, the plurality of bit cells arranged in a plurality of rows and a plurality of columns, each column of the plurality of columns operatively coupled to a pair of bit lines. The apparatus may comprise a controller configured to: assert a word line associated with a row; perform a sequence of write operations while the word line remains asserted, each write operation corresponding to a bit cell associated with a different column of the plurality of columns and the row, wherein the word line has an elevated voltage relative to a non-elevated voltage during at least a portion of the sequence of write operations; and de-assert the word line after the sequence of write operations are performed.

Apparatuses, systems, and methods for data timing alignment in stacked memory. The memory a number of core dice stacked on an interface die. The core and interface die each include adjustable delay circuits along each of a delay and native path. A state machine operates interface and core aligner control circuits to set values of the delay(s) in the interface and core dice respectively. The state machine may initialize the delays and then enter a maintenance state where averaging is used to determine when to adjust the delay in the core dice. If an overflow or underflow condition is met, the state machine may cycle between adjusting the delay in the interface die and adjusting the delays in the core dice without averaging until the overflow and underflow conditions are no longer met and the maintenance state is returned to.

Apparatuses, systems, and methods for read clock timing alignment in a stacked memory. An interface die provides a read clock to a core die. The core die includes a serializer which generates data with timing based on the read clock and an adjustable delay circuit which provides a delayed read clock back to the interface die. The interface die outputs the data with timing based on the delayed read clock received from the core die. In this way, the read clock passes along a return clock path from the interface die, through a delay circuit of the core die and back to the interface die before controlling data output timing. Each core die may adjust the timing of the delay of the read clock in order to better align the read clock with the timing of data provided from that die.

In one embodiment, a method of performing an active polling operation can include: (i) detecting a self-timed operation that is to be executed on a serial memory device; (ii) determining if an active polling mode has been enabled; (iii) determining when the self-timed operation has completed execution on the serial memory device; and (iv) providing a completion indication external to the serial memory device when the self-timed operation has completed execution and the active polling mode is enabled.