A processing device in a memory system receives a data access request identifying a memory cell in a first segment of the memory system comprising at least a portion of at least one memory device. The processing device determines a temperature difference between a current temperature associated with the memory cell and a baseline temperature of the memory system and identifies a temperature compensation value specific to the first segment of the memory system, the temperature compensation value corresponding to the temperature difference. The processing device adjusts, based on an amount represented by the temperature compensation value, an access control voltage applied to the memory cell.

Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of skipped refresh operations on a memory. Memory cells of memories may need to periodically perform refresh operations. In some instances, auto-refresh operations may be periodically skipped when charge retention characteristics of the memory cells of the memory exceed the auto-refresh frequency. To reduce peak current draw during refresh operations, the skipped refresh operations may be staggered across different portions of the memory. In one example, the skipped refresh operation may be staggered in time among memory dies of the memory to limit a number of memory dies that are performing an auto-refresh operation to a maximum number. In another example, the skipped refresh operation may be staggered in time among memory banks of a single memory array to limit a number of memory banks that are performing an auto-refresh operation to a maximum number.

A magnetic configuration utilizing a plurality of posts and spiting the primary winding on each of the posts defining a core and placing the secondary windings together with the rectifier means around each post to minimise the stray and leakage inductance. A significant reduction of the core material and a reduction of the footprint is achieved due to better utilization of the winding material. The magnetic field is weaving from and through one post to the other to minimize the vertical component of ther field and forcing the magnetic field to be parallel with the winding to reduce the AC losses in copper of the winding. These properties allow the magnetic structure to be suitable in very high frequency applications and even in application with an air core. These magnetic structures can be used for implementing a transformer and for inductive applications.

A magnetic configuration utilizing a plurality of posts and spiting the primary winding on each of the posts defining a core and placing the secondary windings together with the rectifier means around each post to minimise the stray and leakage inductance. A significant reduction of the core material and a reduction of the footprint is achieved due to better utilization of the winding material. The magnetic field is weaving from and through one post to the other to minimize the vertical component of ther field and forcing the magnetic field to be parallel with the winding to reduce the AC losses in copper of the winding. These properties allow the magnetic structure to be suitable in very high frequency applications and even in application with an air core. These magnetic structures can be used for implementing a transformer and for inductive applications.

A computing device includes one or more processors, random access memory (RAM), and a non-transitory computer-readable storage medium storing instructions for execution by the one or more processors. The computing device receives first data and classifies the first data using a neural network that includes at least one quantized layer. The classifying includes reading values from the random access memory for a set of weights of the at least one quantized layer of the neural network using first read parameters corresponding to a first error rate.

An apparatus includes a plurality of NAND strings in a block with word lines connected to cells of the NAND strings and select lines connected to select gate transistors of the NAND strings. A control circuit is configured to, after a read operation of memory cells of the block apply substantially zero volts to the global word lines to discharge the word lines to substantially zero volts. The control circuit is further configured to turn off the select gate transistors to isolate channels, turn off the block select transistors to isolate the word lines from the global word lines, and with the block select transistors turned off, apply a low positive voltage on the global word lines.

An apparatus includes a plurality of NAND strings in a block with word lines connected to cells of the NAND strings and select lines connected to select gate transistors of the NAND strings. A control circuit is configured to, after a read operation of memory cells of the block apply substantially zero volts to the global word lines to discharge the word lines to substantially zero volts. The control circuit is further configured to turn off the select gate transistors to isolate channels, turn off the block select transistors to isolate the word lines from the global word lines, and with the block select transistors turned off, apply a low positive voltage on the global word lines.

A semiconductor memory device includes a substrate, a ground selection line, a word line, an insulating layer, a vertical channel portion, and a first peripheral circuit gate pattern. The substrate includes a cell array region and a peripheral circuit region. The ground selection line is on the cell array region. The word line is on the ground selection line. The insulating layer is between the ground selection line and the word line. The vertical channel portion penetrates the ground selection line, word line, and insulating layer in a direction vertical to a top surface of the substrate. The first peripheral circuit gate pattern is on the peripheral circuit region of the substrate. The insulating layer extends from the cell array region onto the peripheral circuit region to cover a top surface of the first peripheral circuit gate pattern.

A random number generator capable of generating a natural random number using a spin-orbit torque (SOT) is provided. The random number generator includes a ferromagnetic metal layer and a spin-orbit torque wiring extending in a first direction crossing a lamination direction of the ferromagnetic metal layer and being joined to the ferromagnetic metal layer, wherein the direction of spins injected from the spin-orbit torque wiring into the ferromagnetic metal layer and an easy magnetization direction of the ferromagnetic metal layer intersect each other.

A magneto-electronic device may include: a spin-orbit torque (SOT) generator layer; a magnetic memory layer; and/or sensing electrodes configured to measure a Hall effect of the magnetic memory layer. The SOT generator layer may include topological insulator material, and the magnetic memory layer may include ferromagnetic material with perpendicular magnetic anisotropy. A magneto-electronic device may include: a spin-orbit torque (SOT) generator layer; a first magnetic memory layer on the SOT generator layer; an insulating layer on the first magnetic memory layer; and/or a second magnetic memory layer on the insulating layer. The SOT generator layer may include topological insulator material. The first magnetic memory layer and the second magnetic memory layer may include ferromagnetic material with either perpendicular magnetic anisotropy or in-plane magnetic anisotropy.