An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

Methods of operating apparatus include receiving user data for programming to a grouping of memory cells of the apparatus, associating an address of the grouping of memory cells with the user data, determining whether power loss to the apparatus is indicated while programming the user data to the grouping of memory cells, and if power loss to the apparatus is indicated while programming the user data to the grouping of memory cells, programming the address of the grouping of memory cells to a different grouping of memory cells of the apparatus. Methods of operating apparatus further include checking whether power loss to the apparatus during programming of user data to a grouping of memory cells of the apparatus is indicated, and, when power loss is indicated, checking feature settings of the apparatus to determine a location of the apparatus containing an address of the grouping of memory cells, and recovering the address of the grouping of memory cells from the determined location.

Disclosed herein is an apparatus that includes: a semiconductor substrate including first and second source regions coupled to a first power supply line and first and second drain regions coupled to a second power supply line, the first drain region being arranged between the first and second source regions, the second source region being arranged between the first and second drain regions; and gate electrodes including a first gate electrode arranged between the first source region and the first drain region, a second gate electrode arranged between the first drain region and the second source region, and a third gate electrode arranged between the second source region and the second drain region. The first and third gate electrodes are supplied with a first control signal. The second gate electrode is supplied with a second control signal.

A memory array includes a first memory cell and a second memory cell, each including a data storage element, a first access transistor coupled to the data storage element, and a second access transistor coupled to the data storage element. The memory array further includes two word lines configured to selectively enable access to the data storage element of the first memory cell through the two access transistors of the first memory cell respectively, two bit lines coupled to the two access transistors of the first memory cell respectively, two another word lines configured to selectively enable access to the data storage element of the second memory cell through the two access transistors of the second memory cell respectively, a third bit line coupled to the first access transistor of the second memory cell, and a first sense amplifier coupled to the first bit line and the third bit line.

A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line precharge circuit generates a precharge voltage for application to each pair of bit lines. The precharge voltage has a first voltage level (not greater than a positive supply voltage for the SRAM cells) when the memory array is operating in a data read/write mode. The precharge voltage has a second voltage level (greater than the first voltage level) in advance of the simultaneous actuation of the word lines for the in-memory compute operation.

Disclosed is a storage device. The storage device includes a nonvolatile memory device that receives write data based on a data strobe signal and a data signal and outputs read data based on the data strobe signal and the data signal, and a controller that performs a training operation for training the nonvolatile memory device to align the data signal and the data strobe signal. The controller detects a left edge of a window of the data signal for the training operation. The controller determines a center of the window by using the detected left edge and unit interval length information of the data signal or determines a start point of a detection operation for detecting a right edge of the window by using the detected left edge and the unit interval length information.

Techniques of processing and/or persistently store data using nanomagnetic elements are disclosed herein. In one example, a processing circuit includes a substrate and a plurality of nanomagnetic elements spaced apart from one another. The plurality of nanomagnetic elements have shape-induced magnetic anisotropy and individually include a geometric center and at least three vertices extending away from the geometric center. One of the nanomagnetic elements has a vertex magnetically coupled to another vertex of another nanomagnetic element such that a magnetic polarity change at the vertex at the one of the plurality of nanomagnetic elements causes a responsive magnetic polarity change at the vertex at the another nanomagnetic element to generate an output of the processing circuit.

Techniques of processing and/or persistently store data using nanomagnetic elements are disclosed herein. In one example, a processing circuit includes a substrate and a plurality of nanomagnetic elements spaced apart from one another. The plurality of nanomagnetic elements have shape-induced magnetic anisotropy and individually include a geometric center and at least three vertices extending away from the geometric center. One of the nanomagnetic elements has a vertex magnetically coupled to another vertex of another nanomagnetic element such that a magnetic polarity change at the vertex at the one of the plurality of nanomagnetic elements causes a responsive magnetic polarity change at the vertex at the another nanomagnetic element to generate an output of the processing circuit.

A non-volatile memory system receives a request to read data. That request includes a quality of service indication. The memory system performs a read process that satisfies the quality of service indication and identifies a set of data with errors. The memory system returns the set of data with errors in response to the request.

Techniques of processing and/or persistently store data using nanomagnetic elements are disclosed herein. In one example, a processing circuit includes a substrate and a plurality of nanomagnetic elements spaced apart from one another. The plurality of nanomagnetic elements have shape-induced magnetic anisotropy and individually include a geometric center and at least three vertices extending away from the geometric center. One of the nanomagnetic elements has a vertex magnetically coupled to another vertex of another nanomagnetic element such that a magnetic polarity change at the vertex at the one of the plurality of nanomagnetic elements causes a responsive magnetic polarity change at the vertex at the another nanomagnetic element to generate an output of the processing circuit.