Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. In some examples, the duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.

It discloses a circuit for reducing a leakage current of a static random access memory (SRAM) memory array and a control method for the same. The circuit includes a memory array power supply voltage control module, a memory array ground terminal voltage control module and a memory array. The present invention controls the voltages on the power supply terminal and the ground terminal of the memory array through the memory array power supply voltage control module and the memory array ground terminal control module, and may reduce the actual data retention voltages of the bitcells, thereby reducing the leakage power of the SRAM in a data retention state. Meanwhile, the present invention implements the function of adjusting the data retention voltage values of the bitcells by controlling different adjustment signals to cope with different design requirements.

Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region, and a body region between the first and second source/drain regions. The body region has a different semiconductor composition than at least one of the first and second source/drain regions to enable replenishment of carrier within the body region. An insulative material is along the body region. A ferroelectric material is along the insulative material. A conductive gate material is along the ferroelectric material.

An electronic device includes a semiconductor memory. The semiconductor memory includes: a write circuit configured to supply a write pulse to at least one of a plurality of memory cells in a write mode, the write pulse corresponding to write data; and a write pulse conversion circuit configured to change a waveform of the write pulse, the waveform having a falling edge, the write pulse conversion circuit changing the falling edge of the wave form to have two or more slopes.

Methods, systems, and devices for techniques to mitigate asymmetric long delay stress are described. A memory device may activate a memory cell during a first phase of an access operation cycle. The memory device may write a first state or a second state to the memory cell during the first phase of the access operation cycle. The memory device may maintain the first state or the second state during a second phase of the access operation cycle after the first phase of the access operation cycle. The memory device may write, during a third phase of the access operation cycle after the second phase of the access operation cycle, the second state to the memory cell. The memory device may precharge the memory cell during the third phase of the access operation cycle based on writing the second state to the memory cell.

The independent claims of this patent signify a concise description of embodiments. Disclosed is technology for reducing write disturbance while writing data into a first SRAM cell and accessing a second SRAM cell in a row of SRAM cells. This Abstract is not intended to limit the scope of the claims.

Disclosed herein is a memory cell arrangement and method thereof for providing a reference read current for reading a plurality of memory cells. The memory cell arrangement includes a plurality of memory cells and one or more reference memory cells. The memory cell arrangement also includes a reference circuit that provides a reference read current for reading one or more of the plurality memory cells, wherein the reference circuit is connected to the one or more reference memory cells to generate the reference read current based on one or more reference currents from the one or more reference memory cells. The memory cell arrangement may also include a shifting circuit connected to the reference circuit, wherein the shifting circuit is configured to shift the reference read current.