A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. The capacitor comprises a first electrode electrically coupled to a source/drain region of the transistor. The first electrode comprises an annulus in a straight-line horizontal cross-section and a capacitor insulator radially inward of the first electrode annulus. A second electrode is radially inward of the capacitor insulator. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. A sense line is electrically coupled to another source/drain region of multiple of the transistors that are in different memory-cell tiers. Additional embodiments and aspects are disclosed, including methods.

Apparatuses, systems, and methods for row hammer based cache lockdown. A controller of a memory may include an aggressor detector circuit which determines if addresses are aggressor addresses or not. The controller may include a tracker circuit which may count a number of times an address is identified as an aggressor, and may determine if the aggressor address is a frequent aggressor address based on the count. If the address is a frequent aggressor address, a cache entry associated with the frequent aggressor address may be locked (e.g., for a set amount of time). In some embodiments, the controller may include a second tracker which may determine if the frequent aggressor address is a highly attacked address. An address mapping associated with the highly attacked address may be changed.

In a method for manufacturing a semiconductor device, a doped region is formed in a substrate from a first main surface. An insulating layer is formed over the doped region of the substrate. Contacts are formed in the insulating layer such that the contacts extend into the doped region. A portion of the substrate is removed from a second main surface. A trench, a first conductive line, and a second conductive line are formed from the doped region of the substrate through etching the substrate from the second main surface. The trench extends through the substrate to expose the insulating layer. The first and second conductive lines are spaced apart from each other by the trench. The contacts are positioned along and in contact with the first and second conductive lines. The trench is filled with a dielectric material.

In a method for manufacturing a semiconductor device, a doped region is formed in a substrate from a first main surface. An insulating layer is formed over the doped region of the substrate. Contacts are formed in the insulating layer such that the contacts extend into the doped region. A portion of the substrate is removed from a second main surface. A trench, a first conductive line, and a second conductive line are formed from the doped region of the substrate through etching the substrate from the second main surface. The trench extends through the substrate to expose the insulating layer. The first and second conductive lines are spaced apart from each other by the trench. The contacts are positioned along and in contact with the first and second conductive lines. The trench is filled with a dielectric material.

To provide a semiconductor device including a first memory cell for holding first analog data, a second memory cell for holding reference analog data, and an offset circuit. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is supplied. The offset circuit supplies a third current corresponding to a differential current between the first current and the second current. The first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is supplied. By subtracting the third current from a differential current between the fourth current and the fifth current, a current that depends on the sum of products of the first analog data and the second analog data is obtained. By providing a plurality of product-sum operation circuits that can be freely connected, a hierarchical neural network can be formed.

In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m_1 or the like). Further, each cell includes selection transistors STr1_n_m and STr2_n_m and an amplifier circuit AMP_n_m that is a complementary inverter or the like is connected to the selection transistor STr2_n_m. Since parasitic capacitance of the sub bit line SBL_n_m is sufficiently small, potential change due to electric charge in a capacitor of each memory cell can be amplified by the amplifier circuit AMP_n_m without an error, and can be output to the bit line.

Methods, systems, and devices for a current monitor for a memory device are described. A memory device may monitor potential degradation of memory cells on the device by monitoring the amount of current drawn by one or more memory cells. As the memory cells degrade, the current supplied to the memory cells may change (e.g., increase due to additional leakage current. The memory device may indirectly monitor changes in the current supplied to the memory cells by monitoring a voltage of a node of a transistor that controls the amount of current supplied to the array of memory cells. The voltage at the control node may be compared to a reference voltage to determine whether the two voltages differ by a threshold amount, indicating that the memory cells are drawing more current. The memory device may output a status indicator when the voltages differ, for example, by the threshold amount.

To increase a storage capacity of a memory module per unit area, and to provide a memory module with low power consumption, a transistor formed using an oxide semiconductor film, a silicon carbide film, a gallium nitride film, or the like, which is highly purified and has a wide band gap of 2.5 eV or higher is used for a DRAM, so that a retention period of potentials in a capacitor can be extended. Further, a memory cell has n capacitors with different capacitances and the n capacitors are each connected to a corresponding one of n data lines, so that a variety of the storage capacitances can be obtained and multilevel data can be stored. The capacitors may be stacked for reducing the area of the memory cell.

The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.

A memory device with a novel structure that is suitable for a register file is provided. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit includes a first logic element and a second logic element each of which is configured to perform logic inversion, a selection circuit, a first switch, a second switch, and a third switch. The second memory circuit includes a first transistor in which a channel formation region is provided in an oxide semiconductor film, a second transistor, and a capacitor to which a potential is supplied through the first transistor.