According to one embodiment, a semiconductor memory device includes a first memory string including a first memory cell transistor, a second memory cell transistor, and a first select element that connects the first memory cell transistor and the second memory cell transistor in series, a second memory string including a third memory cell transistor, a fourth memory cell transistor, and a second select element that connects the third memory cell transistor and the fourth memory cell transistor in series, and a control circuit. The control circuit is configured to set the second select element to an off state while setting the first select element to an on state when reading data of the first memory string.

A semiconductor memory device and a memory system are provided. The semiconductor memory device includes a fingerprint read signal generator configured to generate a fingerprint read signal in response to a refresh counting control signal, a memory cell array comprising a plurality of sub memory cell array blocks, a fingerprint output unit configured to receive data output from memory cells connected to one selected among a plurality of word lines and one selected among a plurality of bit lines of one among the plurality of sub memory cell array blocks in response to the fingerprint read signal to generate fingerprint data, and a pseudorandom number generator configured to perform a linear feedback shifting operation in response to an active command to generate sequence data, receive the fingerprint data in response to the fingerprint read signal, and generate the sequence data based on the fingerprint data.

A memory device includes an open-for-contact region located between the memory blocks, and a row decoder disposed between global lines to which an operating voltage is supplied and the local lines and configured to transfer the operating voltage to one memory block among the memory blocks in response to a row address, wherein a plurality of contacts are formed in the open-for-contact region and configured to transmit a voltage between the bit lines and a peripheral circuit, wherein a dummy region is included in the row decoder and disposed paced apart from the open-for-contact region in the second direction, and wherein a discharge switch is included in the dummy region and configured to discharge the global lines in response to a discharge signal.

Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.

A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.

A metal-insulator-semiconductor-insulator-metal (MISIM) device includes a semiconductor layer, an insulating layer disposed over an upper surface of the semiconductor layer, a back electrode disposed over a lower surface of the semiconductor layer opposing the upper surface, and first and second electrodes disposed over the insulating layer and spaced-apart from each other.

A metal-insulator-semiconductor-insulator-metal (MISIM) device includes a semiconductor layer, an insulating layer disposed over an upper surface of the semiconductor layer, a back electrode disposed over a lower surface of the semiconductor layer opposing the upper surface, and first and second electrodes disposed over the insulating layer and spaced-apart from each other.

Devices and techniques for performing copy-back operations in a memory device are disclosed herein. A trigger to perform a copy-back operation in relation to a section of data stored on the memory device can be detected. Circuitry of the memory device can then read the section of data at two voltage levels within a read window to obtain a first set of bits and a second set of bits respectively. The first and second sets of bits—which should be the same under normal circumstances—are compared to determine whether a difference between the sets of bits is beyond a threshold. If the difference is beyond a threshold, error correction is invoked prior to completion of the copy-back operation.

According to one embodiment, a memory system classifies a plurality of nonvolatile memory dies connected to a plurality of channels, into a plurality of die groups such that each of the plurality of nonvolatile memory dies belongs to only one die group. The memory system performs a data write/read operation for one die group of the plurality of die groups in accordance with an I/O command from a host designating one of a plurality of regions including at least one region corresponding to each die group. The memory system manages a group of free blocks in the nonvolatile memory for each of the plurality of die group by using a plurality of free block pools corresponding to the plurality of die groups.

A semiconductor memory device includes a memory block including a plurality of memory cells programmed to a plurality of program states during a program operation, a voltage generator to generate and apply a program voltage and a select line voltage to the memory block during the program operation, and a read and write circuit to temporarily store program data during the program operation and control a potential of bit lines of the memory block based on the temporarily stored program data. The voltage generator generates the select line voltage as a first select line voltage during a first program operation on some program states among the plurality of program states, or as a second select line voltage for which a potential is lower than a potential of the first select line voltage during a second program operation on remaining program states among the plurality of program states.