Embodiments of the present disclosure are directed toward probabilistic in-memory computing configurations and arrangements, and configurations of probabilistic bit devices (p-bits) for probabilistic in-memory computing. concept with emerging. A probabilistic in-memory computing device includes an array of p-bits, where each p-bit is disposed at or near horizontal and vertical wires. Each p-bit is a time-varying resistor that has a time-varying resistance, which follows a desired probability distribution. The time-varying resistance of each p-bit represents a weight in a weight matrix of a stochastic neural network. During operation, an input voltage is applied to the horizontal wires to control the current through each p-bit. The currents are accumulated in the vertical wires thereby performing respective multiply-and-accumulative (MAC) operations. Other embodiments may be described and/or claimed.

A resistive memory device includes a memory cell array, control logic, a voltage generator, and a read-out circuit. The memory cell array includes memory cells connected to bit lines. Each memory cell includes a variable resistance element to store data. The control logic receives a read command and generates a voltage control signal for generating a plurality of read voltages based on the read command. The voltage generator sequentially applies the read voltages to the bit lines based on the voltage control signal. The read-out circuit is connected to the bit lines. The control logic determines values of data stored in the memory cells by controlling the read-out circuit to sequentially compare values of currents sequentially output from the memory cells in response to the plurality of read voltages with a reference current.

A method for operating a memory device includes sensing a change in temperature of the memory device, adjusting a level of a reference current for a read operation, and reading data from memory cells of the memory device based on the adjusted level of the reference current. The level of the reference current is adjusted from a reference value to a first value when the temperature of the memory device increases and is adjusted from the reference value to a second value when the temperature of the memory device decreases. A difference between the reference value and the first value is different from a difference the reference value and the second value.

A multi-state MRAM device comprises N overlapping ovals defining a free ferromagnetic region. The size of the free ferromagnetic region is controlled the shape anisotropy of the configuration via at least a aspect ratio greater than 2, of the free ferromagnetic region. The free ferromagnetic region has a magnetic moment spontaneously aligned along the long axis in each oval outside the center region. A center magnetic moment has a multitude of exactly 2*N stable orientations determined by the magnetic moments in the segments of the ovals outside the center region. An embodiment is an MRAM device using tunneling junctions to achieve a multi-state memory configuration. Certain embodiments includes an electrically conducting heavy-metal layer disposed adjacent to and connected with the free ferromagnetic region. Some embodiments include a topological insulating material, such as Bi.sub.2Se.sub.3. Magnetic moment reversal in the ovals may be determined by spin-transfer torque associated with the electrically conducting layer.

According to one embodiment, a magnetic memory element includes a stacked structure. The stacked structure includes a first and a second stacked member. The first stacked member includes a first and second ferromagnetic layer. A magnetic resonance frequency of the second ferromagnetic layer is a first frequency. A direction of a magnetization of the second ferromagnetic layer is settable to a direction of a first current when a magnetic field of the first frequency is applied to the first stacked member and the first current flows in the first stacked member. The direction of the magnetization of the second ferromagnetic layer does not change when the second current smaller than the first current flows in the first stacked member. The second stacked member includes a third ferromagnetic layer. A magnetization of the third ferromagnetic layer can generate a magnetic field of the first frequency by the second current.

A method for sensing logical states of memory cells in multiple segments in a memory device, each cell having a high- and low-resistance state, resulting in different cell current levels for the different resistance states. The method includes determining target reference current levels for the respective segments, at least two of the target reference current levels being different from each other; generating a reference current for each segment with the target reference current level for that segment; comparing the cell current level for each cell to the reference current level for the segment the cell is in; and determining the logical states of the memory cells based on the comparison.

An electronic device using an array of magnetic wave guides is shown. In one example a memory device is shown that utilizes spin waves and a magnet storage element that interacts with the spin waves. In one example, an electronic device is shown that utilizes both a complementary metal oxide device and a magnonic device coupled together.

The present invention relates to a semiconductor device. The semiconductor device based on the spin orbit torque (SOT) effect, according to an example of the present invention, comprises the first electrode; and the first cell and the second cell connected to the first electrode, wherein the first and the second cells are arranged on the first electrode separately; the magnetic tunnel junction (MTJ) having a free magnetic layer and a pinned magnetic layer with a dielectric layer in between them; the magnetization direction of the free magnetic layer is changed when the current applied on the first electrode exceeds critical current value of each cell; and the critical current value of the first cell is different from that of the second cell.

A memory device may include a substrate having conductivity regions and a channel region. A first voltage line may be arranged over the channel region. Second, third, and fourth voltage lines may each be electrically coupled to a conductivity region. Resistive units may be arranged between the third voltage line and the conductivity region electrically coupled to the third voltage line, and between the fourth voltage line and the conductivity region electrically coupled to the fourth voltage line. A resistance adjusting element may have at least a portion arranged between one of the resistive units and one of the conductivity regions. An amount of the resistance adjusting element between the first resistive unit and the conductivity region electrically coupled to the third voltage line may be different from that between the second resistive unit and the conductivity region electrically coupled to the fourth voltage line.

Aspects of the present disclosure are directed to magnetic tunnel junction (MTJ) structures comprising multiple MTJ bits connected in series. For example, a magnetic tunnel junction (MTJ) stack according to the present disclosure may include at least a first MTJ bit and a second MTJ bit stacked above the first MTJ bit, and a resistance state of the MTJ stack may be read by passing a single read current through both the first MTJ bit and the second MTJ bit.